raiden00pl
0bed6ac8b4
STM32F33: correct STM32_NDAC
2017-08-20 20:07:50 +02:00
raiden00pl
a8e8862ef9
stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2.
2017-08-20 19:02:56 +02:00
raiden00pl
1479fd6075
stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code
2017-08-20 10:45:55 +02:00
raiden00pl
30ebd32ab4
stm32f33xxx_pinmap.h: missing define
2017-08-20 10:45:55 +02:00
raiden00pl
241c42447f
stm32f33xxx_comp.h: typos
2017-08-20 10:45:55 +02:00
raiden00pl
01c98df18c
STM32F33: remove redundant DAC file
2017-08-20 10:45:55 +02:00
David Sidrane
b594d43d24
Merged in david_s5/nuttx/upstream_dma_dcache_fix (pull request #462 )
...
STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and SDMMC stm32_dma{recv|send}setup
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-17 20:14:24 +00:00
David Sidrane
ef42c25140
stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup
...
In the where CONFIG_SDIO_PREFLIGHT is not used and
dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
boundaries.
2017-08-17 09:51:37 -10:00
David Sidrane
1e7ddfea8e
stm32f7:SDMMC remove widebus limitation on DMA
...
There is no documantation for the STM32F7 that limits DMA on
1 bit vrs 4 bit mode.
2017-08-17 09:48:46 -10:00
David Sidrane
dffab2f4dd
stm32f7:DMA add dcache alignment check in stm32_dmacapable
...
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
2017-08-17 09:39:14 -10:00
David Sidrane
38cbf1f660
stm32f7:DMA correct comments and document stm32_dmacapable
...
Updated comment to proper refernce manual for STM32F7 not
STM32F4.
Added stm32_dmacapable input paramaters documentation.
2017-08-17 09:35:50 -10:00
Gregory Nutt
06a12bea6c
STM32L476VG Discovery: Add a knsh configuration that may be used to test the PROTECTED build mode.
2017-08-17 09:15:12 -06:00
Gregory Nutt
06473e89de
Update MRF24J40 starhub configuration for the SAME70 Xplained.
2017-08-16 09:39:25 -06:00
David Sidrane
5ef33f3e58
Merged in david_s5/nuttx/upstream_missing_semi (pull request #459 )
...
stm32f7:rtc Missing semicolon
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-16 02:49:24 +00:00
David Sidrane
ab578bb338
stm32f7:rtc Missing semicolon
2017-08-15 16:17:55 -10:00
Gregory Nutt
dcb8df76d0
Fix argument to SPI initializatio function
2017-08-15 19:07:35 -06:00
Juha Niskanen
f383308a02
STM32L4 ADC: add ADC register definitions
2017-08-14 06:47:12 -06:00
Juha Niskanen
2fbd7d7b59
STM32L4 DAC: port from STM32. Note that this does not address the somewhat confusing relation between STM32L4_NDACS and DAC2 config macros that comes from original STM32 code.
2017-08-14 06:38:13 -06:00
Juha Niskanen
9ac80e45f5
STM32L4 COMP: input minus pin extended selection
2017-08-14 06:29:13 -06:00
Juha Niskanen
a9343ca12b
stm32/stm32f0: Fix some funny shifts in DAC header files.
2017-08-14 06:28:09 -06:00
Gregory Nutt
e224d354b8
STM32F7: Remove unsupported configuration item the crept in when header file was cloned.
2017-08-13 12:37:59 -06:00
Gregory Nutt
f6f4856cc6
Eliminate some warnings found in build testing.
2017-08-13 12:24:48 -06:00
Gregory Nutt
873de7b480
configs/*/README.txt: Update to the new URL for obtaining the ARM toolchain.
2017-08-13 07:18:19 -06:00
Gregory Nutt
2ab8852b29
STM32F7: Some STM32F7 builds failed in build testing due to undefined STM32_SRAM1_BASE. I think that is because stm32_allocateheap.c was not including chip/stm32_memorymap.h
2017-08-13 06:50:48 -06:00
Gregory Nutt
03c26df04a
STM32F7 builds broken. This is a work around to at least keep them building.
2017-08-13 06:44:04 -06:00
Gregory Nutt
4fa6106b57
Fix some compile problems found in build testing.
2017-08-12 14:28:27 -06:00
Gregory Nutt
1f989af845
Update TODO list; SAMv7 XDMAC: Remove and unused global array.
2017-08-12 12:26:13 -06:00
Gregory Nutt
4b6f0149ec
Eliminate a warning found in build testing.
2017-08-12 11:14:11 -06:00
Gregory Nutt
6bae133e74
Fix two warnings found in build testing.
2017-08-12 11:09:48 -06:00
Gregory Nutt
bd7c84b23e
Remove CONFIG_NETDEV_MULTINIC. This increases code size by a little, but greatly reduces the complexity of the network code.
2017-08-08 14:24:12 -06:00
Stefan Kolb
22dfa875fc
I discovered while working on the SAMV7 mcan driver that the implementation of the CAN error handling is suboptimal. In the current implementation the following errors are implemented as pending errors:
...
* Receiving
* MCAN_INT_STE (Stuff Error)
More than 5 equal bits in a sequence occurred.
* MCAN_INT_CRCE (CRC Error)
Received CRC did not match the calculated CRC.
* MCAN_INT_RF0L (Receive FIFO 0 Message Lost)
Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero.
* MCAN_INT_RF1L (Receive FIFO 1 Message Lost)
Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero.
* Sending
* MCAN_INT_BE (Bit Error)
Device wanted to send a rec / dom level, but monitored bus level was dominant / recessive.
* MCAN_INT_TEFL (Tx Event FIFO Element Lost)
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
* General
* MCAN_INT_MRAF (Message RAM Access Failure)
The flag is set, when the Rx Handler
* has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
* was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation mode (see Section 47.5.1.5). To leave Restricted Operation mode, the processor has to reset MCAN_CCCR.ASM.
* MCAN_INT_ELO (Error Logging Overflow)
Overflow of CAN Error Logging Counter occurred.
The listed errors are not pending, the errors occurred and are gone directly afterwards. This commit changes the described behavior and simplifies the handling of CAN errors.
2017-08-07 10:31:04 -06:00
Jeff
4cbde22992
I'm working on bringing up USB full-speed support on STM32F405. My board does not include a USB power switch, VBus sensing, over current detection, or ID pin.
...
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control. I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet. The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.
These changes let a USB mouse enumerate on my platform if it's plugged in on power-up. Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding. Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything. I'm hoping my issue is something simple I overlooked in configuration.
I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
2017-08-07 10:24:31 -06:00
Simon Piriou
b1f50490bd
MTD: Add driver for Macronix QuadSPI flash memory
2017-08-06 10:51:17 -06:00
Gregory Nutt
42b3ee4cfc
Fix a few errors that crept in with my review changes.
2017-08-02 09:19:29 -06:00
Gregory Nutt
5f2d4b8f84
Changes from review of commit e851a24329
2017-08-02 08:26:08 -06:00
Masayuki Ishikawa
e851a24329
arch/arm/src/lc823450: Initial support for ON Semiconductor LC823450
...
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2017-08-02 21:09:43 +09:00
Titus von Boxberg
55e9c8990c
stm32_rcc: code style
2017-08-01 16:25:19 +02:00
Titus von Boxberg
a4e97d5daf
Added functions for DSI clock source selection
2017-08-01 16:24:48 +02:00
Gregory Nutt
05ea22e9ab
STM32F7: Fix for coding standard violations that came in with cd3ca1140e -- missed a file last time
2017-07-31 18:36:38 -06:00
Gregory Nutt
5f4fdb42be
STM32F7: Fix for coding standard violations that came in with cd3ca1140e
2017-07-31 18:35:37 -06:00
Titus von Boxberg
604a6dc0fa
improved help text
2017-08-01 01:23:28 +02:00
Titus von Boxberg
bdee01f492
added function for reset
2017-08-01 01:23:28 +02:00
Titus von Boxberg
0947b31fbb
STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
2017-08-01 01:23:28 +02:00
Titus von Boxberg
9d56dbb403
comment corrected
2017-08-01 01:23:28 +02:00
Titus von Boxberg
63bce1fc34
no board specific dithering values used; corrected comment; corrected dithering init
2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec95720d13
corrected LIPOS/LIPCR calculation
2017-08-01 01:23:28 +02:00
Titus von Boxberg
28a53d8e25
change only polarity bits in LTDC_GCR
2017-08-01 01:23:28 +02:00
Titus von Boxberg
5de2468521
comments corrected
2017-08-01 01:23:28 +02:00
Titus von Boxberg
69aca28e87
commented
2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec43001d91
HEAP2 depends on CONFIG_ARCH_HAVE_HEAP2, not on particular FMC RAM type
2017-08-01 01:23:28 +02:00
Titus von Boxberg
777b17928f
corrected register debugging
2017-08-01 01:23:28 +02:00
Titus von Boxberg
1944ab6f9b
added missing config option for register value debugging
2017-08-01 01:23:28 +02:00
Titus von Boxberg
dc392a6c68
enable APB2 DSI clock
2017-08-01 01:23:28 +02:00
Juha Niskanen (Haltian)
20dc5ad3b4
STM32L1: add base address for TIM11
...
STM32L4 PWR: correct PWR_SR2 REGLPS and REGLPF bits, add port I registers. Also remove duplicate section from Kconfig
2017-07-31 07:32:43 -06:00
Jeff
a420c0f369
To use an external oscillator module (not just a crystal) with the STM32F4, one needs to enable the HSEBYP bit in the RCC_CR register. This change allows an integrator to define STM32_RCC_CR_HSEBYP in their board.h file if they want this configuration.
2017-07-30 06:22:30 -06:00
Gregory Nutt
47791442a0
Squashed commit of the following:
...
commit 3fcf84a9a2673e1e1466ce5b114d7b73c257e515
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 12:00:31 2017 -0600
Spirit: Brings in the last of the PktCommon interfaces.
commit d26ebd901ba4ba84910e99b4e728b98c30fa4c0b
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:54:52 2017 -0600
Spirit: Add a few more PktCommon interfaces.
commit b5cb8041d50233a4abb8fb4d1dcef5428ae2c2b2
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:33:31 2017 -0600
libc/termios: Remember block comments before empty file sections.
commit 0fcab2c1c8c74442d40bd5e8c6af50a34f8a5821
Author: Sebastien Lorquet <sebastien@lorquet.fr>
Date: Fri Jul 28 09:31:00 2017 -0600
tcdrain implementation based on a new term ioctl
commit 797d4adf7d41068c671f0217d369b797b269de1a
Author: Stefan Kolb <Stefan.Kolb@avat.de>
Date: Fri Jul 28 09:19:04 2017 -0600
We discovered a problem with the samv7 mcan driver which results, under some circumstances, in a very high CPU load.
The problem occurs, and is easily reproducible, if the device is connected to a CAN network with a wrongly configured CAN speed (baud rate). In our tests we set the CAN speed of the device to 1000000 and the speed of the other CAN nodes to 500000. The device is restarted and sends a CANopen “bootup message” to the CAN network. This results in huge amount of errors messages on the CAN bus, probably because of the CAN feature for acknowledging error messages. The error messages can’t be read by the device because of the misconfigured CAN speed, instead the CAN chip reports lots of errors, which are reported to the application which uses the CAN driver (CONFIG_CAN_ERRORS is enabled).
The CAN errors are reported from the CAN chip via interrupts and thus the interrupt load is very high in this scenario. To fix the problem the driver now disables each RX error interrupt after it is occurred. The RX error interrupts are turned back on if at least one CAN message is received successfully.
commit e298f48e96d9e34017dcab8e4d87032862ae9322
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:06:26 2017 -0600
Spirit: Bring in PktStack interfaces.
commit 4a0f00a7058312dcf6ac392689b9f69112f613ec
Merge: 855cf97130 b458934ac4f287cc25d6598386ef90c9ff8cbab92fc0fbcf7e6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-28 12:01:05 -06:00
Gregory Nutt
5f31999b75
Trivial fix to spacing
2017-07-27 11:50:59 -06:00
Titus von Boxberg
28eab902d0
No FSMC, only FMC for STM32F7
2017-07-27 18:27:01 +02:00
Gregory Nutt
2fc0fbcf7e
Squashed commit of the following:
...
commit 89e9d426e91c056e659fccf5e5c4392618f8f777
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:44:19 2017 -0600
Update some comments
commit 9c5d8a5833350006ed389e898b11c8c8a20e5f4f
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:15:54 2017 -0600
Spirit: Rename drivers/wireless/spirit/src to lib. Move Spirit network driver out of IEEE802.15.4 into drivers/wireless/spirit/drivers
commit cabc0ec9e6eb558dcb715ab17264383aa0105e7a
Merge: 87b616414a 6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-24 16:46:30 -06:00
Gregory Nutt
f4e46b0da7
Missed part of 2319ea53a9. Was still getting the warning.
2017-07-22 10:55:54 -06:00
Gregory Nutt
2319ea53a9
STM32L4: Eliminate a warning about implicit definition of function. While we are at it, let's improve the naming a little too.
2017-07-22 09:53:29 -06:00
raiden00pl
f6c1d59531
stm32_hrtim: add slave timers private data, fix some bad definitions, some asserions
2017-07-22 15:14:59 +02:00
Gregory Nutt
c3b552e072
Minor cosmetic updates from review of last PR.
2017-07-20 07:39:57 -06:00
Titus von Boxberg
a20c3b17ce
warning message when using DSI (for debugging)
2017-07-19 20:39:27 +02:00
Titus von Boxberg
7b07471ece
documentation update to f7
2017-07-19 19:14:50 +02:00
Titus von Boxberg
6d29a04752
naming errors/inconsitencies/typos
2017-07-19 19:14:49 +02:00
Titus von Boxberg
1241960d4a
STM32F7: Switch from CCM to DTCM
2017-07-19 19:07:53 +02:00
Titus von Boxberg
071b2dda28
compileable with LTDC_INTERFACE and LTDC_USE_DSI
2017-07-19 19:07:53 +02:00
Titus von Boxberg
e67ba8c88d
option for DSI output
2017-07-19 19:07:53 +02:00
Titus von Boxberg
d590ba7ab2
do not enforce CONFIG_STM32_CCMEXCLUDE for CONFIG_ARCH_CHIP_STM32F7, macro rename STM32 -> STM32F7, #include corrections
2017-07-19 19:07:53 +02:00
Titus von Boxberg
1826c1165a
macro rename STM32 -> STM32F7, #include corrections
2017-07-19 19:07:53 +02:00
Titus von Boxberg
32e417c3ac
renamed STM32_LCDTFT_BASE to STM32_LTDC_BASE for consistency
2017-07-19 19:07:53 +02:00
Titus von Boxberg
58053fef0f
macro rename STM32 -> STM32F7
2017-07-19 19:07:53 +02:00
Titus von Boxberg
ec3e4cabab
added config and make stuff for stm32f7 ltdc
2017-07-19 19:07:53 +02:00
Titus von Boxberg
ea703b832a
copied from stm32
2017-07-19 19:07:53 +02:00
Titus von Boxberg
07531de2e4
Copied files from stm32
2017-07-19 19:07:53 +02:00
Matt Thompson
eff9ba514c
SAMD21: Changes needed to get USB working.
2017-07-19 07:22:14 -06:00
Titus von Boxberg
f3267ddb71
I2C4_SDA can also be on GPIO PB7
2017-07-18 11:43:53 +02:00
savinz
1b27dd32af
STM32 F7 Ethernet: Fix typo in header; Add memory sync barrier between writing to DMA TX descriptor and restarting DMA TX. Avoid calling work_queue on pollwork if it's already queued, just skip a poll cycle instead. Nucleo-144: Fix RMII TXD1 signal, connected to PB13 not to PG14.
2017-07-14 09:23:43 -06:00
Gregory Nutt
447785b264
SAMD/L21: Need to preserve errno value across syslog() call.
2017-07-12 16:22:23 -06:00
Gregory Nutt
10fbb2b089
SAMD/L21 USB: Remove all commented out logic.
2017-07-12 08:10:21 -06:00
Janne Rosberg
76ea6f09ec
SAMD/L21: Add a USB driver. Developed for Filament Inc. by Offcode, LTD.
2017-07-12 07:46:46 -06:00
Matt Thompson
5448c99ff2
I was having issues with the bus freezing up .. slaves holding SDL low.. so I rewrote a good portion of the interrupt logic based on the application notes from Atmel. One major improvement is using the RXNACK flag in the STATUS register, which indicates that no device responded to an address packet. Assuming that the chip will always give an interrupt status, I believe it's possible to eliminate the timer as well.
2017-07-12 06:44:53 -06:00
Matt Thompson
1e0560b22f
SAMD21: Fix some SPI-related issues.
2017-07-11 12:48:38 -06:00
Gregory Nutt
839019f305
SAMD/L21 I2C: Another update... needs to use enter/leave_critical_section vs. old irqsave/restore.
2017-07-11 07:01:05 -06:00
Alan Carvalho de Assis
5b9526b4c1
SAML21 I2C driver. Developed for and contributed with permissin from Filament company.
2017-07-11 06:58:58 -06:00
Gregory Nutt
79e5d2b7b6
STM32 TIM3/4 are always 16-bits; never 32-bits. Noted by Eetu Nevalainen.
2017-07-10 13:56:06 -06:00
Gregory Nutt
76587b2c6f
STM32 Kconfig: 'unfold' some of the dependencies to provide better long term configuration support. This also effective reverts the recent 15b85738e7
2017-07-06 10:34:54 -06:00
Gregory Nutt
47be509d79
Rename CONFIG_STM32_STM32F40XX to CONFIG_STM32_STM32FXXXX since it is used by F4 parts other than F40x
2017-07-06 10:20:14 -06:00
gwenhael.goavec
15b85738e7
In arch/arm/src/stm32/Kconfig when the CPU is a STM32F4, some STM32_HAVE_xx with xx = {OTGFS, TIM3, TIM4, SPI3, I2S3, I2C3} are selected by default. But for F410 these peripherals are absent. This change add tests to check if the target CPU is an F410 or not and selects according to the situation. This also adds a select for STM32_HAVE_DAC1 present on this STM32 flavor.
2017-07-06 09:52:21 -06:00
Eetu Nevalainen
21dcc8cbc7
stm32f40xxx_rtcc ISR register and write protection fix
2017-07-03 11:06:07 -06:00
Gregory Nutt
68315b7444
Merged clang into master
2017-07-03 07:04:57 -06:00
Gregory Nutt
09ab651e02
samv71-xult: Add support for the MRF24J40 radio and create a mrf24j40-starhub configuration. A few fixes to IPv6 and 6LoWPAN were required to have 6LoWPAN and Ethernet coexisting. Untested and expect some complexity in the bring-up.
2017-07-02 11:04:57 -06:00
Gregory Nutt
cf44fd6ec0
Add CLANG definitions in Kconfig and Toolchain.defs
2017-07-02 06:42:48 -06:00
Gregory Nutt
1c5ec07414
arch/: Remove dangling space at the end of lines.
2017-06-28 13:16:48 -06:00
Gregory Nutt
aa1708e7c0
6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver.
2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff
stm32f33xxx_rcc: cleanup + move hrtim clock source selection
2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd
stm32f33xxx_rcc.h: fix typo
2017-06-26 18:26:59 +02:00
Juha Niskanen
56eeb40958
STM32L4 serial: Allow configuring Rx DMA buffer size
2017-06-26 09:19:42 -06:00
Juha Niskanen
90ccdf287d
STM32 L4 DMA: Correct USART3_RX bad channel definition
2017-06-21 08:40:33 -06:00
