Commit Graph

22531 Commits

Author SHA1 Message Date
8fd5bf9ec2 Adding build intructions to reproduce bug. 2024-11-16 15:31:33 +01:00
xuxingliang
dceb26c7b2 drivers/segger: add heap data plot
Add heap current used to note.
Plot it in segger sysview data plot.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-25 19:04:02 +08:00
xuxingliang
7e89ff5d11 sched/note: add note when mm add new region
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-25 19:04:02 +08:00
xuxingliang
c2bcc56546 sched/note: specify note event for heap instrumentation
1. Add NOTE_HEAP_ prefix for heap note event.
2. Use note type as heap instrumentation parameter.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-25 19:04:02 +08:00
yinshengkai
2c0e2ac36b note: add memory tracing event support
Record all memory allocation and release, save to ram, used to analyze memory allocation rate and memory usage
Its absolute value is not trustworthy because the memory will be allocated in thread A and released in thread B

 netinit-5   [0]   0.105984392: tracing_mark_write: C|5|Heap Usage|96|free: heap: 0x606000000020 size:24, address: 0x603000000370
 netinit-5   [0]   0.105996874: tracing_mark_write: C|5|Heap Usage|24|free: heap: 0x606000000020 size:72, address: 0x6070000008e0
nsh_main-4   [0]   3.825169408: tracing_mark_write: C|4|Heap Usage|2177665|free: heap: 0x606000000020 size:424, address: 0x614000000840
nsh_main-4   [0]   3.825228525: tracing_mark_write: C|4|Heap Usage|14977|free: heap: 0x606000000020 size:2162688, address: 0x7f80a639f800
nsh_main-4   [0]   3.825298789: tracing_mark_write: C|4|Heap Usage|15189|malloc: heap: 0x606000000020 size:20, address: 0x6030000003a0

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-25 19:04:02 +08:00
lijianjun
803489b546 add mm_uninitialize empty implementation for sim
Signed-off-by: lijianjun <lijianjun@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-25 19:04:02 +08:00
xuxingliang
17cbaadce8 task: use get_task_name where possible
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-25 19:04:02 +08:00
hujun5
9dc3e4ee41 arm64: fix fvp smp faild to boot
reason:
we should give a busy wait addr

This commit fixes the regression from https://github.com/apache/nuttx/pull/13640

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 18:04:49 +08:00
hujun5
6e7d90e195 arm64: remove the operation of clearing interrupts during GIC initialization
To align with the implementation of ARMv7-A, remove the operation of clearing
interrupts during GIC initialization to avoid losing interrupts during asynchronous startup.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 18:04:49 +08:00
hujun5
956d77ba23 arm64:add busy wait flag
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 18:04:49 +08:00
hujun5
6dd26a3e68 arm64/smp: changing the startup of arm64 SMP from serial to parallel
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 18:04:49 +08:00
ligd
9a317472fd arm-m: support zero interrupt back to game
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-18 23:54:11 +08:00
ligd
946b01d4a8 arm-M: set current regs for crash dump
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-18 23:54:11 +08:00
ligd
8b8a2610ab armv6/7/8m: use pendsv to handle context switch
This PR support Nested interrupt in armv6/7/8m:

There are two types of nested interrupt model:

Zero latency nested interrupt
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x50
High irq1           0x60             ISR can't access system API
irq_save()          0x70
High irq2           0x80             ISR can't access system API
normal irq3         0xB0
We have already support this mode before this PR

Nested interrupt which interrupt level lower than up_irq_save()
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x70
irq_save()          0x80
High irq1           0x90              ISR can access system API
High irq2           0xA0              ISR can access system API
normal irq3         0xB0
Now, this PR can support this mode

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-18 23:54:11 +08:00
ligd
064415a765 armv6m: add up_trigger_irq() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-18 23:54:11 +08:00
ligd
aa4a428825 armv7/8m: unmask all the IRQ when thread start
NVIC_SYSH_PRIORITY_MIN not the basepri loweest prio
spec says:
basepri 0 - Disables masking by BASEPRI

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-18 23:54:11 +08:00
hujun5
33e30239f1 sched: replace sync pause with async pause for nxtask_terminate
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-17 12:51:14 +02:00
Alin Jerpelea
1b64c80d72 Revert "sim: fix context-switch when do wdog callback()"
This reverts commit a3568af10551c37b839169634c33fbe78044725f.
2024-10-17 12:51:14 +02:00
hujun5
cedcb1a674
sim: add NXSYMBOLS pthread_gettid_np pthread_self
reason:
enable sim:smp can boot

This commit fixes the regression from https://github.com/apache/nuttx/pull/12561

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-16 11:27:30 +02:00
hujun5
b1932c668d sim: fix sim smp boot regression
This commit fixes the regression from https://github.com/apache/nuttx/pull/13716

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
c35e25b7e5 arch: rename xxxx_pause.c to xxxx_smpcall.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
d54bc8a9f8 arch: remove up_cpu_pause up_cpu_resume up_cpu_paused up_cpu_pausereq
reason:
  To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
  after that we need to further implement "schedlock + spinlock".
changelist
  1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
  2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
  3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
  4 change up_cpu_pause_async to up_send_cpu_sgi

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
6392d5a6b3 xtensa: Replace the implementation of up_cpu_pause
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
fbed4ece2c x86_64: we should call x86_64_restorestate/x86_64_savestate
reason:
In x86_64, g_current_regs is still used for context switching.

This commit fixes the regression from https://github.com/apache/nuttx/pull/13616

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
p-szafonimateusz
f5a449487c arch/intel64: colorize IDLE stack for AP cores
colorize IDLE stack for AP cores in x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
4a796c39bb xtensa: add parameters to xtensa_pause_handler
reason:
nxsched_smp_call_handler need these parameters

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
p-szafonimateusz
e0d9cc432c arch/intel64: fix IRQ conflict with GOLDFISH
Also move MSI IRQ definition to place where other IRQ definitions are.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
4fd92edee7 sched: replace sync pause with async pause for nxsig_process
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
487fcb3bce signal: adjust the signal processing logic to remove the judgment
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
8275a846b1 arch: move sigdeliver to common code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-11 01:30:51 +08:00
buxiasen
ec58a6ab25 arch: cpu pause when sigaction only necessary if tcb running
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-11 01:30:51 +08:00
p-szafonimateusz
fad4232925 arch/x86_64/intel64/intel64_schedulesigaction.c: properly align signal handler stack for vector operations
signal handler stack must be properly aligned, otherwise vector instructions doesn't work in signal handler

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-11 01:30:51 +08:00
p-szafonimateusz
a33528fa4a arch/x86_64/intel64/intel64_cpuidlestack.c: stack_alloc should point to stack base not stack top
stack_alloc should point to stack base not stack top

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-11 01:30:51 +08:00
p-szafonimateusz
bbea8dcefe arch/x86_64/intel64/intel64_head.S: move initial RSP for AP cores below regs area
move initial RSP for AP cores below regs area.
otherwise IDLE thread for AP cores can be corrupted

XCP region now match regs allocation in up_initial_state()

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-11 01:30:51 +08:00
Ville Juven
192dde1b58 arm64_task/pthread_start: Set sp_el0 upon starting user process
As the handling of sp_el0 was moved from the context switch routine
to exception entry/exit, we must set sp_el0 explicitly when the user
process is first started.
2024-10-11 01:30:51 +08:00
lipengfei28
7975c94d88 Kernel build: enter exception save sp_sl0,exit exception restroe sp_el0
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-11 01:30:51 +08:00
ligd
669cd3aa2c arm64: simply the vectors
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-11 01:30:51 +08:00
ligd
7cbcf82bed arm64: save FPU regs every time
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-11 01:30:51 +08:00
qinwei1
d782f6c1ac arm64: add arm64_current_el to obtain current EL
Summary
  Add a macro to obtain current execute level

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2024-10-11 01:30:51 +08:00
qinwei1
40d40015f4 arm64: refine the fatal handler
Summary
  The original implement for exception handler is very simple and
haven't framework for breakpoint/watchpoint routine or brk instruction.
  I refine the fatal handler and add framework for debug handler to
register or unregister. this is a prepare for watchpoint/breakpoint
implement

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2024-10-11 01:30:51 +08:00
hujun5
542e46319c xtensa: g_current_regs is only used to determine if we are in irq, with other functionalities removed.
reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs

before
text    data     bss     dec     hex filename
178368     876  130604  309848   4ba58 nuttx
after
text    data     bss     dec     hex filename
178120     876  130212  309208   4b7d8 nuttx

szie change -248

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-10 15:31:50 +02:00
ligd
a9df7f0d1e xtesa: fix lost save & restore states caused by merge code
this is caused by:
35c8c80a00a99ff0e19d51eaa74165bd830a36f8

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 15:31:50 +02:00
ligd
1fb4f8f50e arch: change nxsched_suspend/resume_scheduler() called position
for the citimon stats:

thread 0:                     thread 1:
enter_critical (t0)
up_switch_context
note suspend thread0 (t1)

                              thread running
                              IRQ happen, in ISR:
                                post thread0
                                up_switch_context
                                note resume thread0 (t2)
                                ISR continue f1
                                ISR continue f2
                                ...
                                ISR continue fn

leave_critical (t3)

You will see, the thread 0, critical_section time is:
(t1 - t0) + (t3 - t2)

BUT, this result contains f1 f2 .. fn time spent, it is wrong
to tell user thead0 hold the critical lots of time but actually
not belong to it.

Resolve:
change the nxsched_suspend/resume_scheduler to real hanppends

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 15:31:50 +02:00
hujun5
2f4c067c50 fix compile error:
Register: smp
Register: nsh
Register: sh
Register: getprime
Register: ostest
Espressif HAL for 3rd Party Platforms: b4c723a119344b4b71d69819019d55637fb570fd
common/xtensa_cpupause.c: In function 'xtensa_pause_handler':
common/xtensa_cpupause.c:240:3: warning: implicit declaration of function 'xtensa_savestate'; did you mean 'xtensa_setps'? [-Wimplicit-function-declaration]
  240 |   xtensa_savestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~
      |   xtensa_setps
common/xtensa_cpupause.c:243:3: warning: implicit declaration of function 'xtensa_restorestate'; did you mean 'xtensa_context_restore'? [-Wimplicit-function-declaration]
  243 |   xtensa_restorestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~~~~
      |   xtensa_context_restore

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-10 15:31:50 +02:00
Yongrong Wang
c48f158e66 arm_gicv2.c: fix armv7a compile error
/vela/nuttx/drivers/pci/pci_ecam.c:432:(.text.pci_ecam_get_irq+0x16): undefined reference to `up_get_legacy_irq'

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
2024-10-10 15:31:08 +02:00
lipengfei28
7cf9b73f18 arm64 pci legacy irq do not support yet
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-10 15:31:08 +02:00
lipengfei28
1cb81f9a8f armv7a pci irq support
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-10 15:31:08 +02:00
lipengfei28
519c5c86aa add pci irq interface
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-10 15:31:08 +02:00
wangyongrong
db95659a9c x86_64_pci.c: x86_64_pci_read/write_io memory support
Signed-off-by: wangyongrong <wangyongrong@xiaomi.com>
2024-10-10 15:31:08 +02:00
yezhonghui
52ffca5b8e arm64 support gicv2m for pci irq
Signed-off-by: yezhonghui <yezhonghui@xiaomi.com>
2024-10-10 15:30:00 +02:00