Gustavo Henrique Nihei
a0617177e8
risc-v/esp32c3: Fix inclusion of C++ constructors/destructors table
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RISC-V GCC is configured with --enable-initfini-array so it emits an
.init_array section instead of .ctors
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Dong Heng
698f1f76ff
risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash
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This can fix BLE assert when erase SPI Flash.
2021-12-06 13:13:11 +09:00
Abdelatif Guettouche
60da4317b9
arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for
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consistency.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
f54804bafc
arch/risc-v/esp32c3: Create a separate heap for the RTC memory.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
bd0e03fecf
boards/risc-v/esp32c3-devkit/esp32c3.ld: Add the RTC BSS section for
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completeness.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
61f7bc6e2a
boards/risc-v/esp32c3-devkit/scripts: Drop the "iram" in the name of the RTC
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section.
The RTC region is accessed by both I and D buses. The old name of
`rtc_iram_seg` is a bit confusing.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Gustavo Henrique Nihei
ba23526e39
boards/esp32c3-devkit: Allocate .noinit in a dedicated section
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Previously it was being allocated into .bss section after the _ebss
address. Although functional, this is not intuitive.
2021-04-28 15:40:49 +01:00
Dong Heng
458caf2732
riscv/esp32c3: Add ESP32-C3 WLAN netcard driver
2021-03-16 10:42:32 -03:00
Gustavo Henrique Nihei
7fe096c65e
risc-v: Fix typos reported by codespell
2021-02-25 16:25:47 +00:00
Abdelatif Guettouche
5562f08369
boards: Add the ESP32-C3 DevKit board
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00