22530 Commits

Author SHA1 Message Date
Huang Qi
fc5a029e44 riscv: Unify the extended context save/restore
This patch unifies the extended context save/restore for RISC-V,
allowing the customized context save/restore to be used, for example,
the extended context in rv32m1.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-11 19:50:07 +08:00
Ville Juven
48f545d54a arm64/crt0.c: Fix stack alignment when executing signal trampoline
The stack alignment requirement is 16-bytes, not 8-bytes.
2024-09-11 19:49:24 +08:00
Tiago Medicci Serrano
f063e47c28 espressif: Update external libraries to fix GPIO interrupt bug
This commit updates the HAL version used by NuttX to fix the bug
reported in https://github.com/apache/nuttx/issues/13303
2024-09-11 09:05:45 +08:00
Ville Juven
132868b728 arm64_syscall.c: Don't need to set register context during syscall
The register context is not needed, the original idea was to provide
the user stack pointer for signal handler delivery, but the user stack
can be obtained via sp_el0 so the context registers are not needed.

SP0 is not stored upon exception entry anyways, so this code is just
completely redundant and wrong.
2024-09-10 23:23:21 +08:00
hujun5
1aab457b4c sched:add parameters to restore_critical_section
reason:
In SMP, when a context switch occurs, restore_critical_section is executed.
To reduce the time taken for context switching, we directly pass the required
parameters to restore_critical_section instead of acquiring them repeatedly.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-10 23:14:09 +08:00
Ville Juven
0ca1a07e84 arm64_addrenv_pgmap.c: Revoke user execution access to kernel mmap'd pages
Otherwise, user can run code from there
2024-09-10 23:10:57 +08:00
Ville Juven
eebff25d69 arm64_mmu.h: Change ordering of access flags for user data
This makes it more readable, no functional changes
2024-09-10 23:05:12 +08:00
Ville Juven
080f9ede45 arm64_mmu.c: Fix kernel L1 page table size
The kernel L1 page table must be at least 1 page
2024-09-10 23:05:12 +08:00
Ville Juven
4149e45450 arm64_mmu: Fix TLBI instruction format
The vaddr field in TLBI means: Bits[55:12] of the virtual address to match.
This basically means the page offset of the virtual address, so the input
vaddr must be shifted to the page offset.

Reference TLBI VALE1IS register description from ARMv8-A reference manual.
2024-09-10 23:05:12 +08:00
Ville Juven
fbc796cff1 arm64_mmu: Do not set accessed-flag for table descriptors
The 12:0 bits in table descriptors are RES0 and AF is the 10th bit, so
it is not valid to set it in this case.

Fix this by moving AF to the common MMU_MT_NORMAL_FLAGS field
2024-09-10 23:05:12 +08:00
Ville Juven
00c4da73b3 arm64_addrenv.c: Flush kernel page table copy to user mappings
Make sure the user L1 page is updated to system memory when the kernel
mappings are copied.

Also, flush the I-cache when switching address environments.
2024-09-10 22:56:06 +08:00
Ville Juven
20ce41d080 arm64_vector_table.S: Remove unnecessary instruction
The expression "sub    x0,  x0,  * XCPTCONTEXT_GP_REGS" is void,
as the next instruction overwrites x0 anyway.
2024-09-10 22:55:12 +08:00
shizhenghui
7472b08851 sim_sound: add AUDIOUTILS_LAME to dependency list
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
shizhenghui
dea9e5343d arch/sim/Makefile: add libmad & lame include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
shizhenghui
6637606096 sim_offload: move out of the posix directory
The libmad and libmp3lame libraries have been ported to
apps/audioutils and will be compiled with NuttX.

Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
cuiziwei
6eb286ae01 sim:Remove -lmad cause it has been ported to the apps/audioutils directory.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-09-10 20:25:48 +08:00
Bowen Wang
bf5c571098 arm64/qemu_boot: add arm64 pci io memory map
and rename other pci region name to make them more
readable

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang
b12fa7f760 qemu_boot: change IVSHMEM memory region to PCI memory region
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang
99876fa529 arm64/mmu_region: add ivshmem mmu region for arm64
Now the ivhsmem memory region can be used in arm64

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
yangshuyong
6a09037efd arm64/qemu_boot: add the pcie cfg address for arm64
1. Extend the arm64 address to 48bit;
2. Add pci cfg address to the mmu map table;

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
2024-09-10 14:34:31 +08:00
Stuart Ianna
f69a62583c arch/risc-v/src/litex: Update parameter to match new register typedef.
This silences the warning produced after the uintreg_t definitions was introduced in 8ebc3aa9e83374caf39ee5137c082854de2f10ab.
2024-09-10 14:03:16 +08:00
Stuart Ianna
f96370700e arch/risc-v/src/litex/litex_serial: Fix build warning after inline spinlock change.
Resolves regression introduced in a4fece3450be99fbca5815558dec9374d4ee04e3.
2024-09-10 14:03:16 +08:00
adriendesp
42f471ba4d Fix xmc4_spi.c DX select.
Added option to have different DX for each USIC channel.
2024-09-10 11:36:59 +08:00
meijian
a7224cf35a net/netstatistics: add tx/rx bytes statistics for dev
We can see them in ifconfig:

ap> ifconfig
wlan0   Link encap:Ethernet HWaddr 42:64:7f:b3:12:03 at UP mtu 1500
        inet addr:10.0.1.2 DRaddr:10.0.1.1 Mask:255.255.255.0
        inet6 DRaddr: ::

        RX: Received Fragment Errors   Bytes
            00000b9b 00000000 00000000 21daf5
            IPv4     IPv6     ARP      Dropped
            00000a33 00000137 00000031 00000000
        TX: Queued   Sent     Errors   Timeouts Bytes
            00000ac4 00000ac4 00000000 00000000 1a2103
        Total Errors: 00000000

Signed-off-by: meijian <meijian@xiaomi.com>
2024-09-10 11:36:03 +08:00
yanghuatao
c43c91816d toolchain/ghs: add ghs link script for mps2-an500 platform
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-09-09 01:26:13 +08:00
George White
3f00c4aae0 rp2040: support pico-sdk 2.0.0
Since the introduction of the rp2350, the pico-sdk project has been
re-arranged and elf2uf2 has been merged in to a new 'picotool' binary
which is supplied and installed separately.
2024-09-08 21:43:22 +08:00
p-szafonimateusz
882c0d0a47 arch/x86_64: convert all asm() to __asm__()
asm() is not supported by -std=c99, __asm__() is more portable

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-07 01:01:24 +02:00
YAMAMOTO Takashi
8b81689f2c Appease a GCC warning
```
common/xtensa_swint.c:442:24: error: passing argument 1 of 'up_dump_register' discards 'volatile' qualifier from pointer target type [-Werror=discarded-qualifiers]
  442 |       up_dump_register(CURRENT_REGS);
      |                        ^~~~~~~~~~~~
```
2024-09-06 21:17:57 +02:00
ouyangxiangzhen
dc7d3470e6 arch/x86_64: Fix wrong RDTSCP implementation
RDTSCP instruction reads the current value of the processor’s
time-stamp counter (a 64-bit MSR) into the EDX:EAX registers, and it
also reads the value of the IA32_TSC_AUX MSR (address C0000103H) into
the ECX register. However, the current RDTSCP implementation does not
provide a hint for the compiler that ECX has been changed, resulting in
register corrupted and subtle errors.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-06 17:27:20 +02:00
ouyangxiangzhen
f6e4ab25bd arch/x86_64: Support QEMU PVH ELF loader
Enabling CONFIG_ARCH_CHIP_INTEL64_PVH_BOOT will allow nuttx.elf loaded by QEMU -kernel parameter.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-06 20:56:46 +08:00
yangshuyong
7cbb7d36d8 Changed the x86 64 pci driver
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
Filipe Cavalcanti
2af7037fa1 xtensa/esp32s2: add WiFi support on ESP32S2 2024-09-06 09:46:59 +08:00
Filipe Cavalcanti
4915338857 xtensa/esp32s2: fix for timers and watchdog init on startup 2024-09-06 09:46:59 +08:00
Filipe Cavalcanti
2e884cbd11 xtensa/esp32s2: add support for shutdown handlers 2024-09-06 09:46:59 +08:00
yinshengkai
6ac1299218 nrf91: fix cmake compiler error
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-09-06 09:42:53 +08:00
hujun5
608b59e401 smp: enable smp_call in all smp arch
reason:
In subsequent implementations, we will replace up_cpu_pause with smp_call.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-06 07:11:38 +09:00
hujun5
ea181e2621 arm: armv7-a/r and armv8-r up_cpu_index inline
reason:
inline small code to improve performance

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-06 03:44:49 +08:00
yinshengkai
da6ddea8d4 arch/arm: support kernel heap in BUILD_FLAT mode
Make umm & kmm heap alloc more clear, and possible support FLAT build to
enable kernel heap.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-09-05 11:19:47 -03:00
chao an
dedb4c95c9 armv8-r/r52: add neon support into compiler line
1. correct the armv8-r fpu flag from vfpv3-d16 to fpv5-sp-d16
2. add neon support

This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.

Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.

Reference:
https://developer.arm.com/Processors/Cortex-R52

Instruction set:

Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point
Unit either with single-precision or double precision and Neon.

Signed-off-by: chao an <anchao@lixiang.com>
2024-09-05 09:52:51 -03:00
tfzou
fad8a22074 arm: Add support for CSK6011A SOC and CSK6011A-NANO board
Signed-off-by: tfzou <tfzou@listenai.com>
2024-09-05 09:34:33 -03:00
hujun5
198630a809 sched: use this_task replace nxsched_self
reason:
We can reduce a function call to improve performance.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 09:33:50 -03:00
fangxinyong
7b05a550dc sched: replace up_cpu_index with this_cpu
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-09-05 12:09:24 +08:00
YAMAMOTO Takashi
fb58ac99fa esp32_psram.c: Remove a seemingly stale comment 2024-09-05 11:49:31 +08:00
chao an
2465b67c84 cmake/tricore: filter out nostdlib in linker phase to avoid build break
Regression by:

| commit b64fb09e6c688fcb94877048e99dbc2173d24c3b
| Author: xuxin19 <xuxin19@xiaomi.com>
| Date:   Tue Jul 16 15:50:13 2024 +0800
|
|     cmake:bugfix fix CMake LTO build block
|
|     it was wrong in https://github.com/apache/nuttx/pull/12423/files#r1618852245
|     EXTRA_FLAGS is useful in LTO for pass option tu lto linker
|
|     Signed-off-by: xuxin19 <xuxin19@xiaomi.com>

Signed-off-by: chao an <anchao@lixiang.com>
2024-09-05 11:47:06 +08:00
Kevin Zhou
fc6bcd6600 xtensa/esp32s3: Add timing delay set interface for QSPI 2024-09-05 11:36:18 +08:00
chao an
6098747c4f arm/giv3: add g_ prefix to some global variables
Signed-off-by: chao an <anchao@lixiang.com>
2024-09-05 09:58:21 +08:00
YAMAMOTO Takashi
3d275bd4a2 psram_cache_init: remove cosmetic differences between PRO/APP
No functional changes are intended.
2024-09-05 09:44:18 +08:00
hujun5
433f159c06 arch: remove unused up_cpu_pausereq waiting
reason:
After the up_cpu_pause call completes, it guarantees that other CPUs have fully stopped.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-05 07:15:54 +09:00
Yanfeng Liu
7bd857c9f1 Revert "arch/riscv: unify in-kernel syscall"
This reverts commit 6986cd4105 as it breaks critical section as in
https://github.com/apache/nuttx/pull/12864#issuecomment-2325779041
2024-09-04 09:47:49 -03:00
YAMAMOTO Takashi
58d3c53d2e esp32: fix seemingly wrong calculations
DPORT_APP_CACHE_MASK_DRAM1 is already a mask.
2024-09-04 09:15:16 +02:00