This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
The 1170 usage of the GPR registers is to select the
between GPIO{2|3} or CM7_GPIO{2|3} where as the 1060
it selected ports between 1-6,2-7..4-9 and uses
different GPR registers.
For the 1170 we are defaulting to GPIO{2|3} and not
supporting the swtich to CM7_GPIO{2|3}.
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
imxrt:Kconfig fix formatting
imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map
imxrt:lpspi Fix build breakage from adding 1170
imxrt:Finish 1170 iomux and clockconfig versioning
imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4
imxrt:pmu remove duplicate dcd non 117x header
imxrt:lpspi Fix unused var warnings
imxrt:lpi2c Fix unused var warnings
imxrt:lowputs Fix unused var warnings
imxrt:imxrt117x_dmamux fix duplicate entries
imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them
imxrt:MPU Support the 1170
imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE
imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity
Author: Peter van der Perk <peter.vanderperk@nxp.com>
IMXRT7 Add LPUART 9/10/11/12 support
Author: David Sidrane <david.sidrane@nscdg.com>
imxrt:1170pinmux Add QTIMER pins
imxrt:1170pinmux Add GPT pins
imxrt:1170pinmux Add FLEXPWM pins
imxrt1170:pinmap Add GPIO_ENET_1G pinning
imxrt:enet Support ENET_1G
imxrt:periphclks rt1170 does not have canX_serial clock
imxrt:flexcan:Layer imxrt_ioctl
imxrt117x:memorymap added CAN3
imxrt:ADC support ver1 and ver2 for imxrt117x
imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn
imxrt:imxrt117x_ccm align CCM names with rt106x
imxrt:XBAR support larger number of selects needed on imxrt1170
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
FlexSPI AHB Region support, PIT rename for compatiblity
imxrt:USB Analog add VBUS_VALID_3V
FlexSPI expand prefetch registers for IMXRT117X
imxrt:Support Initialization of FlexRam without Running from OCRAM
imxrt: ocotp add UNIQUE_ID register definition
imxrt: enet use ocotp unique_id
imxrt: enet fixes for imxrt117x
imxrt: ethernet pinmux sion enable
imxrt:imxrt_periphclk_configure add memory sync
Flush the pipeline to prevent bus faults, by insuring a
peripheral is clocked before being accessed on return from
this function.
imxrt:Restructure gpioN to padmux mapping
imxrt:Add imxrt1170 daisy
imxrt: correct power modes for imxrt117x fixing hang on WFI
imxrt: imxrt117x TCM MPU config
imxrt: FlexRAM clocking DIV0 setup
imxrt: 117x periphclocks wait for status bit
imxrt: iomucx set pad settings correctly and allow reconfiguration
imxrt: enet align buffers 64-byte for optimal performance
Add DSC barriers for write-through cache support
imxrt: imxrt1170 use FlexCAN FD/ECC features
imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS
imxrt:Fix 1170 SNVS addressing
imxrt: enet set mii clock after ifdown so that phy keep working
nxstyle fixes
imxrt: preprocessor and include fixes
Fix configs
imxrt1170-evk clean defconfig
Fixes is stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 660ac6, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
chip/sam_emac.c:3754:11: error: 'struct sam_emac_s' has no member
named 'phytype'
3754 | if (priv->phytype == SAMV7_PHY_KSZ8061)
| ^~
make[3]: *** [Makefile:167: sam_emac.o] Error 1
Member phytype is available only if CONFIG_NETDEV_PHY_IOCTL and
CONFIG_ARCH_PHY_INTERRUPT is set.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fixes stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 8362e314, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
This prevents dma stop operations called of a completion
call back from rentering, the callback and ensures that
the call back will see the idle state.
1. Configurable mapping of virtual address to psram physical address
2. Access SPIRAM memory at high physical address through bank switching
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Since picolibc used by clang-17 does not provide an implementation of libm,
if you want to use clang, please must specify a libm as an option.
Signed-off-by: chao an <anchao@xiaomi.com>
armv6-m/arm_dumpnvic.c: In function 'arm_dumpnvic':
armv6-m/arm_dumpnvic.c:67:13: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv6-m/arm_dumpnvic.c:67:27: note: format string is defined here
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ~~~^
| |
| unsigned int
| %08lx
Signed-off-by: chao an <anchao@xiaomi.com>
chip/stm32_ethernet.c:2014:7: warning: variable 'i' set but not used [-Wunused-but-set-variable]
2014 | int i;
| ^
1 warning generated.
Signed-off-by: chao an <anchao@xiaomi.com>
To avoid losing the first frame, the set_buf needs to excute first. At the same time, imgdata->start_capture should excuted before the imgsensor->start_capture.
Signed-off-by: yaojingwei <yaojingwei@xiaomi.com>
The divider should be rounded to the next full integer to ensure that
the resulting SPI frequency is <= target frequency, i.e. the SPI is
not overclocked.
After this, RISC-V fully supports the kmap interface.
Due to the current design limitations of having only a single L2 table
per process, the kernel kmap area cannot be mapped via any user page
directory, as they do not contain the page tables to address that range.
So a "kernel address environment" is added, which can do the mapping. The
mapping is reflected to every process as only the root page directory (L1)
is copied to users, which means every change to L2 / L3 tables will be
seen by every user.
