Commit Graph

41 Commits

Author SHA1 Message Date
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Huang Qi
ef3219e83d boards: Refresh all configs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Huang Qi
0c28fe9831 boards: Remove unused NXFLAT flags from Make.defs
Since NXFLAT only avaliable on arm.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-27 11:08:43 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Ville Juven
356ae984ac Add knsh target for icicle
Template for knsh target (e.g. protected build with user space nsh)

Requires MPU and linker script updates to work
2022-01-25 20:22:34 +08:00
Eero Nurkkala
e5a9ba5602 risc-v/mpfs: opensbi defconfig: refresh config
Some of the configuration options have changed, so update this
config file accordingly.

In this example config, the following hart configuration takes
place:
  hart1: 0xafb00000 (Another NuttX)
  hart2: unused
  hart3: 0x80200000 (u-boot and Linux kernel)
  hart4: 0x80200000 (u-boot and Linux kernel)

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Xiang Xiao
04297c3ca3 board: Remove -fno-omit-frame-pointer from Make.defs
except sim arch, since this flag is set inside Toolschain.defs now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Xiang Xiao
8bcdefafc9 board: Remove -fno-strength-reduce
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-19 00:14:03 +01:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
Eero Nurkkala
c67a1a4de1 risc-v/mpfs: ld-envm-opensbi.script: add all opensbi code to .text.sbi
Add the rest of the OpenSBI code to .text.sbi -section. They belong
to there. This frees up some space in the very limited eNVM.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Eero Nurkkala
76c6ccc732 risc-v/mpfs: opensbi/defconfig fix RAM start address
RAM is expected to start from 0x08000000, not from
0x80000000 in this case. DDR starts from 0x80000000.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Eero Nurkkala
b4d2944df7 tools/mpfs: prepare OpenSBI image
Polarfire Icicle board has only (128K - 256) bytes for the bootloader
in the non-volatile eNVM. This space is barely enough for running NuttX.
If OpenSBI is selected, it will be placed in DDR. This all means the
nuttx.bin file grows into gigabyte size, filling the unused space (ddr -
envm) with zeroes.

The memory layout is as follows:

MEMORY
{
    ddr  (rx)          : ORIGIN = 0x80000000, LENGTH = 4M
    envm (rx)          : ORIGIN = 0x20220100, LENGTH = 128K - 256
    l2lim  (rwx)       : ORIGIN = 0x08000000, LENGTH = 1024k
    l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k
}

OpenSBI library is used as a separate binary, which is stored into
eMMC or SD-card. It is then loaded into its precise location in DDR.

Thus, we separate OpenSBI from NuttX and end up with two images
by utilizing the objcopy options:

  --only-section=sectionpattern (-j in short)
  --remove-section=sectionpattern (-R in short)

This is only valid when CONFIG_MPFS_OPENSBI is set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-04 19:45:14 +08:00
Jukka Laitinen
6f413c8654 board icicle/opensbi: Reduce image size slightly
Drop somme fancy nsh features

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
ligd
412d030149 boards: move USERMAIN_XX out of INIT_ENTRYPOINT
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-12-24 08:23:30 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Jukka Laitinen
ac5a228d89 boards/risc-v/mpfs: Enable CONFIG_SPI_CS_CONTROL
Enable CS control via register write for the mpfs hwtest target

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Xiang Xiao
ea0aadff1e boards/mpfs: Fix the icicle build break
src/mpfs_emmcsd.c: In function 'mpfs_board_emmcsd_init':
Error: src/mpfs_emmcsd.c:72:40: error: 'SDIO_SLOTNO' undeclared (first use in this function)
   finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
                                        ^~~~~~~~~~~
src/mpfs_emmcsd.c:72:40: note: each undeclared identifier is reported only once for each function it appears in
Error: src/mpfs_emmcsd.c:83:55: error: 'SDIO_MINOR' undeclared (first use in this function); did you mean 'SHRT_MIN'?
   finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-18 11:45:50 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2021-11-18 10:59:44 -03:00
Eero Nurkkala
8e43f39141 mpfs: cache: provide L1/L2 cache enablers
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-04 11:00:55 -03:00
Jani Paalijarvi
a16a9f80e2 mpfs: i2c: Add support for adaptive I2C bus frequency
Select the closest possible frequency which is smaller
than or equal to requested in I2C msg
2021-11-02 04:10:08 -05:00
Eero Nurkkala
c7cf9fd9d2 mpfs: board Make.defs: add bootloader linker option
Use the linker script used with bootloaders that start
from the eNVM.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Eero Nurkkala
ad76b6733c mpfs: boards: add ld-envm.script
This configuration is used when flashing nuttx as a bootloader
in the eNVM region.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Eero Nurkkala
3b330089d5 mpfs: ddr: add DDR training
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.

DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:

  envm (rx)   : ORIGIN = 0x20220100, LENGTH = 128K - 256
  l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k

256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git

For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:

 cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
 cat nuttx.bin >> nuttx_bootloader.bin
 riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
  *+0x20220000 nuttx_bootloader.bin flashable_image.hex

This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Janne Rosberg
e022ea1283 mpfs/icicle/configs/hwtest: enable SD card 2021-09-18 12:18:09 -03:00
Eero Nurkkala
812f504c16 mpfs: emmcsd: add Kconfig/Makefile and board files
Add necessary Kconfig, Make.defs, Makefile and board
file changes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-09-18 12:18:09 -03:00
Janne Rosberg
d361a9ded8 boards/icicle: add hwtest config
This config enables all peripherals and some tools.
Also useful for CI build check.
2021-09-11 23:33:01 +08:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
2021-08-20 08:56:30 -03:00
Xiang Xiao
b12f588140 Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL
since boardctl isn't a libc feature

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-06 13:58:26 +02:00
Xiang Xiao
5025fbef8d Rename LIB_ to LIBC_ for all libc Kconfig
follow other libc component naming convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-05 19:45:24 +02:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-29 21:55:21 -03:00
Jiuzhu Dong
85470176e7 sched/task: delete CONFIG_MAX_TASKS limit
Change-Id: I583015a95dbcebd352f81ecb3104ffdbd646a9ec
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-07-11 19:42:30 -07:00
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-06-11 21:03:42 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-06-11 09:10:03 -05:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-01 06:42:02 +09:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-05-24 22:55:44 -05:00