sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
37,187 Commits 1 Branch 0 Tags 291 MiB
8b289023bf
Commit Graph

8 Commits

Author SHA1 Message Date
Gregory Nutt
c2244a2382 Remove CONFIG_TLS 
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
 2020-05-07 12:04:16 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Yang Chung-Fan
8b86fae8d3 arch: x86_64: Check only XSAVE and rename __eanble_sse3 to __enable_sse_avx 2020-05-05 02:03:34 -07:00
Yang Chung-Fan
2936f72651 arch: x86_64: revoke lower 128MB mapping later, ldmxcsr require 32-bit address 2020-05-05 02:03:34 -07:00
Brennan Ashton
aea90e7cf0 Clean code to match nxstyle requirements 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Brennan Ashton
a9871f584a Resolve linking issues with x86_64 port 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-05-04 08:32:22 -06:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly 
This typo had been copied and pasted into numerous irq and syscall
headers.
 2020-04-05 22:31:15 +01:00
Sonic Yang
b984752aec Flat address x86_64 port of Nuttx (#411) 
* arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer

* arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2

* arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly

* arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling

* arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure

* arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method

* arch: x86_64: Fix C alias of page table and GDT/IST

* arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup

* arch: x86_64: Consolidate MSR definition in arch/arch.h

* arch: x86_64: Edit the way of handling GDT/IST in C into structures

* arch: x86_64: Correct the starting point of isr/irq stack

* arch: x86_64: Update up_initialize.c with the new initializing procedure

* arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT

* arch: x86_64: Overhual of interrupt initialization procedure

* arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory]

* arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure

* arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug

* arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot

* arch: x86_64: Correctly apply license header, comment and format code

* arch: x86_64: properly send a SIGFPE on floating point error

* arch: x86_64: Remove unused variable in up_restore_auxstate

* arch: x86_64: properly trash the processor with an infinite loop

* arch: x86_64: Fix typo in ISR handler causing ISR not handled

* arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path

* arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE

* arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method

* board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support

* arch: x86_64: update defconfigs

* arch: x86_64: rename qemu as qemu-intel64

* arch: x86_64: update Board readme
 2020-03-03 19:02:59 -06:00