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20 Commits

Author SHA1 Message Date
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place 
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-07-04 13:25:56 +03:00
Masayuki Ishikawa
5a9b2920e8 arch: risc-v: Add support for semihosting and hostfs 
Summary:
- This commit adds support for semihosting and hostfs

Impact:
- None

Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-05-02 19:46:58 +08:00
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode 
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm" 
This reverts commit 9b7f9867aa.
 2022-05-01 11:31:01 +03:00
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-04 12:05:53 +08:00
Xiang Xiao
629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall 
follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-25 10:26:15 -03:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 22:51:00 +02:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg 
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h 
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 11:47:42 +08:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-28 00:30:10 -06:00
Alin Jerpelea
231b8518b7 NuttX: Ken Pettit: update licenses to Apache 
Ken Pettit has submitted the ICLA and we can migrate the licenses
 to Apache.

Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly 
This typo had been copied and pasted into numerous irq and syscall
headers.
 2020-04-05 22:31:15 +01:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189) 
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
 2020-01-31 09:24:49 -06:00
Masayuki Ishikawa
e33fc3dc89 Squashed commit of the following: 
Author: Gregory Nutt <gnutt@nuttx.org>

    Run all .c and .h modified in PR through nxstyle.

Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>

    feature k210 (#16)

    * arch: risc-v: Add support for __LP64__ to types.h
    * arch: risc-v: Add support for RV64GC to common files
    * arch: risc-v: Add support for Kendryte K210 processor (RV64GC)
    * boards: risk-v: Add support for Sipeed Maix Bit with K210
    * tools: Add support for Kendryte K210 processor
 2019-12-31 09:06:20 -06:00
Ken Pettit
201a32cf8c Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it. 2016-10-16 09:47:07 -06:00