cpu0 thread0: cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
IRQ enter
arm64_pause_handler()
enter_critical_section() begin
up_cpu_paused() pick thread0
arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
thread0 -> thread1
arm64_syscall()
case SYS_switch_context
change thread0 tcb->xcp.regs
restore_critical_section()
enter_critical_section() done
leave_critical_section()
IRQ leave with restore CURRENT_REGS
ERROR !!!
Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.
Resolve:
Move arm64_restorestate() after enter_critical_section() done
This is a continued fix with:
https://github.com/apache/nuttx/pull/6833
Signed-off-by: ligd <liguiding1@xiaomi.com>
Use private naming to avoid conflicts with user applications
In file included from libuv/src/unix/internal.h:25,
from libuv/src/unix/udp.c:23:
libuv/src/uv-common.h:57: warning: "container_of" redefined
57 | #define container_of(ptr, type, member) \
|
In file included from nuttx/include/nuttx/list.h:47,
from nuttx/include/nuttx/tls.h:40,
from nuttx/include/nuttx/sched.h:48,
from nuttx/include/nuttx/arch.h:87,
from nuttx/include/nuttx/userspace.h:35,
from nuttx/include/nuttx/mm/mm.h:30,
from nuttx/include/nuttx/kmalloc.h:34,
from nuttx/include/nuttx/lib/lib.h:31,
from nuttx/include/stdio.h:35,
from apps/system/libuv/libuv/include/uv.h:59,
from libuv/src/unix/udp.c:22:
nuttx/include/nuttx/nuttx.h:48: note: this is the location of the previous definition
48 | #define container_of(ptr, type, member) \
|
Signed-off-by: chao an <anchao@lixiang.com>
change optimization to -Os for CONFIG_DEBUG_FULLOPT to be compatible with other architectures
and add an option to select CONFIG_DEBUG_CUSTOMOPT
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
enable FPU and implement up_fpucmp to pass ostest
With aggressive optimization enabled (-O2/-O3), ostest FPU test will fail.
This is because the compiler will generate additional vector
instructions between subsequent up_fpucmp() calls (loop vectorization
somewhere in usleep() call), which will consequently overwrite
the expected FPU context (XMM registers).
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
1. Fix issue of system blocking due to disable dcache.
2. Support Ext-SRAM-Cache mmu mapping in SMP mode.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
__revoke_low_memory() is called in intel64_lowsetup()
fixes b4b96a6435 (PR #11758) in which the multiboot2 header was accessed
after revoking the low memory which caused page fault.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
The stack pointer must be aligned to 16 bytes, otherwise the system crash on the first unaligned data access with vector instruction.
The problem is only observable with optimization enabled, when vector instructions are generated.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
this is a follow up to the change from 2335b69120 which missed
updating stack frame length for this memset
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
During removal of F1 related stuff, code that configures FLASH
latency was removed, which rendered some of the F3 line unbootable.
It was done by mistake, since previous removed block was
'#ifdef VALUE_LINE', and block with FLASH code was '#ifndef VALUE_LINE'
and so it should not have been removed.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Add support for tricore TC397
1. Porting based on AURIX TC397 KIT_A2G_TC397_5V_TFT evaluation board
https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft/
2. In order to avoid license and coding style issues, The chip-level code
still uses the implementation of AURIX Development Studio SDK.
The SDK package will be downloaded as a third-party package during compilation:
https://github.com/anchao/tc397_sdk
3. Single core only, SMP implementation will be provided in the future.
4. Implemented the basic System Timer, ASCLIN UART driver.
5. Only the Tasking tool chain is supported (ctc/ltc, license maybe required)
6. 'ostest' can be completed on the TC397 development board.
How to run?
1. Setup the tasking toolchain and license
$ export TSK_LICENSE_KEY_SW160800=d22f-7473-ff5d-1b70
$ export TSK_LICENSE_SERVER=192.168.36.12:9090
2. Build nuttx ELF
$ ./tools/configure.sh tc397/nsh
$ make -j
...
artc I800: creating archive libc_fpu.a
LD: nuttx
3. Switch to windows PC, setup AURIX-studio to Debugger Launcher
4. Replace runing ELF to nuttx, and re-download ELF
Signed-off-by: chao an <anchao@lixiang.com>
This patch adds inter-processor interrupt support using K230 mailbox
device to improve the RPMsg efficiency. The polling logic has been
dropped.
Major changes:
- in arch/risc-v/include/k230:
- irq.h add IRQ for IPI devices
- in arch/risc-v/src/k230:
- Kconfig add IPI related config, increase polling delay
- Make.defs add k230_ipi.c to CHIP_SRCS
- k230_hart.c fix typo, add notes of zero MISA reading w/ NUTTSBI
- k230_irq.c use K230_PLIC_IRQS as ext IRQ limit to support IPI
- k230_rptun.c use IPI instead of polling
- in boards/risc-v/k230/canmv230/configs
- master enable IPI support
- remote enable IPI, TMPFS, RPMSGFS etc
New additions:
- in arch/risc-v/src/k230:
- k230_ipi.h add K230 IPI related defintions
- k230_ipi.c add K230 IPI driver
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
-- Detecting CXX compile features
-- Detecting CXX compile features - done
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
arm-none-eabi-gcc: error: -Wstrict-prototypes: No such file or directory
-- Configuring done
-- Generating done
Signed-off-by: chao an <anchao@lixiang.com>
The board's microphone uses 24-bit i2s and this commit also fixes
the segmentation fault caused by the audio buffer overflow.
arch/xtensa/src/esp32/esp32_i2s.c: Fix bug regarding 24-bit audio and add AUDIOIOC_STOP to ioctl
drivers/audio/audio_i2s.c: Report number of channels on AUDIOIOC_GETCAPS
in boards/xtensa/esp32/esp32-sparrow-kit:
/configs/nsh/defconfig: Add I2S configs
/src/esp32-sparrow-kit.h: Add the signature of esp32_i2sdev_initialize()
/src/esp32_bringup.c: Add call to esp32_i2sdev_initialize()
Signed-off-by: simonatoaca <simona.alexandra2000@gmail.com>
This commit implements the RMT peripheral for all the supported
Espressif's RISC-V devices. It also implements the support for the
WS2812 addressable RGB LED using the RMT peripheral.
WS2812 data is encoded into RMT items according to the RMT clock
source. This commit makes it by using the actual clock source in
spite of a pre-defind value.
- remove read-write logic - this should be handled by radio protocol implementation
- remove EVENTS and TASKS bit definitions - we can just use a signle definition
- add more radio ops
- fix frequency configuration
- fix printf warnings
- fix radio reset
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
I noticed when executing pwm STOP command in
multichannel mode, the channel still outputting.
This commit fixes this issue.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This patch revises `k230_hart.[ch]` by:
- revising big core boot/stop control.
- making k230_hart_is_big() available in S-mode.
- adding more comments.
This patch also revises the `ld-kernel.script` so that to match the
latest MMU pgtable design.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.
New additions:
- in arch/risc-v/src/k230
- k230_rptun.c K230 RPTUN driver
- k230_rptun.h K230 RPTUN driver header file
- in baords/risc-v/k230/canmv230
- configs/master Build config for master node
- configs/remote Build config for remote node
- scripts/ld-rptun.script Build script for RPTUN
Major changes:
- arch/risc-v/Kconfig Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
- k230/irq.h Add UART3 IRQ defs
- in arch/risc-v/src/k230
- Kconfig Add RPTUN related config items
- Make.defs Add k230-rptun.c to sources
- hardware/k230_memorymap.h Add K230 device and CSR defs
- k230_hart.c Add hart ctrl for RPTUN
- k230_hart.h Add hart ctrl for RPTUN
- k230_mm_init.c Add Svpmbt to support RPTUN
- k230_start.c Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
- scripts/Make.defs Add RPTUN script selection
- src/canmv_init.c Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
- index.rst Add AMP usage information.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
I recently imported NuttX version 6.0 (and nsh) into a Microchip
Studio project [1] on Windows to figure out what was going wrong with
the avr32dev1 build. I also briefly checked NuttX version 10.
I worked with the assumption that the avr32 (avr32dev1) specific
changes to the codebase were minimal across NuttX releases.
For the initial proof of concept I used Microchip Studio version 7.0
(with the recent Microchip's ASF updates). I use avr32-gcc (4.4.7)
hosted here [2] for building NuttX for avr32dev1 on GNU/Linux.
Even with the Microchip Studio project, I had initial debug problems
with just stepping through the code a line at a time. I had to bring
in crt0, a trampoline stub and the linker file from one of my older
projects to really build on the suspicion I had with the linker file.
Perhaps an older version of avr32-gcc did something differently. I am
not sure about this. I used avr32-objdump to see the output sections
of the generated elf file. I just had to tweak the linker script to
ensure correct linking of the sections.
With those changes, I was able to inspect the UART sections within
NuttX Microchip Studio project.
Second important change: the transmit pin: I had to reassign the pin
to see the nsh console.
These are the currently assigned UART pins:
RX: PA_24 -> Physical IC pin 59
TX: PB_02 -> Physical IC pin 24
For the avr32dev1 board, they are pins: J1 (berg pin 28) and J2 (berg
pin 10).
In addition, the PR fixes silly compilation problems with avr32dev1.
I have tested the nsh build with my avr32dev1 boards. I used Atmel ICE
to program one of them (flash at 0x80000000) and dfu-programmer to
test my other board (flash at 0x80002000). The other RS-232 parameters
are the same as they were.
References:
[1]: https://github.com/ramangopalan/nuttx_avr32dev1
[2]: https://github.com/ramangopalan/avr32-gnu-toolchain-linux_x86_64
SAMv7 reset controller stores the cause of last reset (SW reset, power up,
pin reset etc.) in status register. This commit adds function that allows
the board to retrieve this information. This function should be called
from board support layer either during initialization or based on
incoming ioctl call.
Adding the sam_get_reset_cause() to sam_systemreset.c also resulted in
always compiling this file by default and only putting up_systemreset()
under CONFIG_SAMV7_SYSTEMRESET option.
Also header file sam_systemreset.h was created as it defines reset types
in comfortable manner for future processing in board layer. This is done
to avoid passing boardctl dependent structure to architecture layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
By setting "isconsole" to false, mpfs_serial stops outputting to console.
This can be used to disable output to debug console in low level.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It is possible that a PLIC IRQ is claimed but not completed at warm
reset. This occurs at least if there is a fault in the middle of irq
handler execution.
To recover from such situation, we can complete all IRQ:s in PLIC;
this completes any already claimed IRQ, but has no effect on IRQs
which are not claimed or not enabled.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block
- Use the i2c mutex to protect the reset; in case there are several devices
on the same bus, and one of them resets the bus, reset must not occur in
the middle of another device's transfer.
- Move irq attach to the i2c_init as the irq detach is in i2c_deinit
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.
Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0
Resolution 8 bits = values 0~255
Voltage: 0~Vref
The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The RPTUN_PING option has been replaced by RPMSG_PING but this
use for PERF_EVENTS is left behind, so replace it here as well.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.
Within folder `arch/risc-v/src/k230`:
- Changes:
- CMakeLists.txt add k230_hart.c to sources list
- Make.defs add k230_hart.c to sources list
- chip.h add inclusion to k230_hart.h etc
- k230_irq.c move sbi_late_init() to k230_hart.c
- k230_start.c add support to run on big core
- hardware/:
- k230_memorymap.h add T-Head C908 specific CSR
- Additions:
- k230_hart.c sbi_late_init w/ hart initialization
- k230_hart.h header file
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.
Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
Commit 03e5c02 introduced option to have both standard SPI and QSPI
in SPI mode on one system. However this change broke the appearance of
QSPI driver configuration menu entry in menuconfig as it was dependent
on !SAMV7_QSPI_IS_SPI (which is now true for all MCUs having standard
SPI ability in QSPI driver).
This change makes sure the menu is correctly shown when QSPI driver
used.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
