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20013 Commits

Author SHA1 Message Date
Xiang Xiao
d5689e070b net/arp: Remove nuttx/net/arp.h 
1.move ARPHRD_ETHER to netinet/arp.h
1.move arp_entry_s to net/arp/arp.h
2.move arp_input to nuttx/net/netdev.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-12-16 22:10:59 +02:00
zhangyuan21
453a1a7332 arch: move stack and task dump to common code 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2022-12-17 01:59:35 +08:00
Gustavo Henrique Nihei
7114cc2978 risc-v/esp32c3: Revert aes_cypher name change introduced in #6920 
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-12-16 16:19:47 +02:00
zhangyuan21
632d87ee71 arch: remove up_release_pending function 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2022-12-16 21:29:57 +08:00
Peter van der Perk
19ca5ecbb0 Fix S32K1XX PM which was broken by #7869 2022-12-16 20:37:47 +08:00
Peter Bee
aeed8f5d26 include/nuttx/video: remove validate_buf 
Removing validate_buf since it's only locally called in driver

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2022-12-16 17:03:35 +08:00
Peter Bee
71c34d6391 sim/video: call validate_buf when set_buf 
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2022-12-16 17:03:35 +08:00
Lucas Saavedra Vaz
077c790830 arch: Make REG_[GET/SET]_FIELD thread safe for ESP SOCs 2022-12-16 13:32:43 +08:00
David Sidrane
707ac4b8f6 s32k1xx:Apply style changes from code review 
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-12-16 01:06:12 +08:00
David Sidrane
75baa5b932 s32k1xx:LPSPI use DMA 2022-12-16 01:06:12 +08:00
David Sidrane
89f99dceed s32ke3xx:EDMA Usage Clean up 2022-12-15 22:21:32 +08:00
David Sidrane
df4eb4896d s32k3xx:LPSPI register usage cleanup 2022-12-15 22:21:32 +08:00
Petro Karashchenko
949a0d6032 arch/arm: remove FAR from ARM files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-12-15 11:38:17 +08:00
Petro Karashchenko
e9fe00c573 arch/renesas: remove FAR and apply formatting 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-12-15 11:38:17 +08:00
Almir Okato
8f3c425067 xtensa/esp32s3: Enable booting from MCUboot bootloader 
Add support for booting from MCUboot bootloader on ESP32-S3.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
 2022-12-15 00:42:13 +08:00
Peter van der Perk
d172d8cd0f S32K FlexCAN don't use a blocking wait in tx avail 2022-12-14 10:45:43 -05:00
Lucas Saavedra Vaz
773e3fad43 arch/xtensa/esp32: Add initial support for touch pad polling 2022-12-14 22:38:10 +08:00
Lucas Saavedra Vaz
b8ef8daef9 arch/xtensa/esp32: Add missing macros to iomux 2022-12-14 22:38:10 +08:00
Lucas Saavedra Vaz
2280b33eea arch/xtensa/esp32: Add functions to get RTC clock 2022-12-14 22:38:10 +08:00
Lucas Saavedra Vaz
f9a9512d3c arch/xtensa/esp32: Fix typo in SENS registers 2022-12-14 22:38:10 +08:00
Lucas Saavedra Vaz
15dadd0099 arch/xtensa/esp32: Remove redundant RTC registers 2022-12-14 22:38:10 +08:00
Lee Lup Yuen
b895207489 arm64/a64: Add driver for MIPI DSI 
This PR adds the driver for Allwinner A64's MIPI Display Serial Interface (DSI) and MIPI Display Physical Layer (D-PHY).

This driver will be used by the upcoming Display Driver for PINE64 PinePhone.

- `include/nuttx/crc16.h`: Added 16-bit CRC-CCITT

- `libs/libc/misc/Make.defs`: Added 16-bit CRC-CCITT to Makefile

- `arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > MIPI DSI" (`CONFIG_A64_MIPI_DSI`), which enables the MIPI DSI Driver

- `arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for MIPI DSI

- `arch/arm64/src/a64/Make.defs`: Added the MIPI DSI Driver to the Makefile

- `libs/libc/misc/lib_crc16ccitt.c`: Compute 16-bit CRC-CCITT

- `arch/arm64/src/a64/mipi_dsi.c`, `mipi_dsi.h`: Compose MIPI DSI Packets (Long, Short, Short with Parameter)

- `arch/arm64/src/a64/a64_mipi_dsi.c`, `a64_mipi_dsi.h`: MIPI DSI Driver for Allwinner A64

- `arch/arm64/src/a64/a64_mipi_dphy.c`, `a64_mipi_dphy.h`: MIPI D-PHY Driver for Allwinner A64

- `platforms/arm/a64/boards/pinephone/index.rst`: Added MIPI DSI as supported peripheral for PinePhone

Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-12-14 22:37:32 +08:00
David Sidrane
1760057e29 s32k1xx:Apply Style Changes from code review 
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-12-14 21:03:31 +08:00
David Sidrane
592e946bdf 32k1xx:serial:Support GPIO (buffler level) Flow control 2022-12-14 21:03:31 +08:00
David Sidrane
5a948ed3dd 32k1xx:serial fix HW Handshaking 2022-12-14 21:03:31 +08:00
David Sidrane
9bb1226b04 s32k1xx:serial Add EDMA 2022-12-14 21:03:31 +08:00
David Sidrane
8a412ba59b s32k1xx:Refactor DMAMUX for s32k11x, s32k14x 2022-12-14 21:03:31 +08:00
anjiahao
bc0fe0ea16 crypto:add some hardware support 
esp32c3: aes hmac-sha1 hmac-sha256
stm32f0l0g0 stm32l1 : aes
sam34: aes
lpc43: aes
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-12-14 02:33:56 +08:00
anjiahao
2b071b7a42 arch/armv8m:support pmu api 
The register definition comes from CMSIS
https: //github.com/ARM-software/CMSIS_5
commit id:10bf763a82318c0c852ff9ecc2d5cd8cebe7d761
file: Core/Include/pmu_armv8.h
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-12-14 00:27:02 +08:00
David Sidrane
4284d0398b imxrt:Serial LPUART_STAT_PF s/b LPUART_STAT_NF 
as a result of a typo LPUART_STAT_NF was not checked and
   cleared on LPUART_STAT_PF.
 2022-12-14 00:26:42 +08:00
Peter van der Perk
6b3b5751c1 S32K automatically calculate size of periphclocks array 2022-12-13 19:50:01 +08:00
chao an
47fbfa215e fs/hostfs: mode_t of mkdir(2) should use the nuttx prototype 
Signed-off-by: chao an <anchao@xiaomi.com>
 2022-12-13 18:16:20 +08:00
chao an
aad16d16e2 sim/windows: add hostfs support for windows 
Signed-off-by: chao an <anchao@xiaomi.com>
 2022-12-13 18:16:20 +08:00
田昕
0382b63f5d move common assert logic together. 
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
 2022-12-12 17:05:02 +08:00
chao an
61563d6004 risc-v/es32c3: improve passthrough performance by iob offload 
Use iob offload model to improve passthrough performance

1. Use iob buffer instead of reserved packet buffer
2. Enable TCP/UDP buffer mode

-------------------------------------------------
|  Protocol      | Server | Client |            |
|-----------------------------------------------|
|  TCP           |    7   |    12  |  Mbits/sec |
|  TCP(Offload)  |   17   |    11  |  Mbits/sec |
|  UDP           |   10   |    16  |  Mbits/sec |
|  UDP(Offload)  |   43   |    28  |  Mbits/sec |
-------------------------------------------------

Signed-off-by: chao an <anchao@xiaomi.com>
 2022-12-11 16:19:20 +08:00
Peter Bee
a5a1a68a25 arch/sim: add v4l2 driver for sim 
communicate with Linux host v4l2 drivers

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
 2022-12-09 23:37:49 +08:00
Gustavo Henrique Nihei
9af5dca7dc risc-v/esp32c3: Refactor and rename linker scripts 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-12-09 11:19:27 +08:00
zhangyuan21
ffd2eb5b14 arch/arm: only compare callee-saved registers for fpu 
Registers S0-S15 (D0-D7, Q0-Q3) do not need to be preserved. They can be used for passing
arguments or returning results in standard procedure-call variants.
Registers D16-D31 (Q8-Q15), do not need to be preserved.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2022-12-09 11:00:38 +08:00
Alan Carvalho de Assis
fbdd246878 esp32: Fix maximum I2C FIFO size (now SSD1306 will work) 2022-12-09 02:23:28 +08:00
wangbowen6
27ea9f7625 arm/Kconfig: add cortex-m85 config 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-12-09 01:53:10 +08:00
Gustavo Henrique Nihei
236ee5c80d xtensa/esp32: Rename linker scripts into more meaningful names 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-12-08 21:55:29 +08:00
wangbowen6
c44f87eb1a arm: add syscall SYS_save_context support for old arm and armv7-r 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-12-08 12:37:29 +08:00
TimJTi
18482efc39 SAMA5D2 fix printf formatter 
Update sam_adc.c

Update sam_adc.c

%08x -> PRIx32

More %08x

Revert incorrect change (PRIx32)

Update sam_tc.c

Update sam_tc.c

more style corrections/typos

Update arch/arm/src/sama5/sam_adc.c

Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
 2022-12-07 21:33:17 +01:00
zouboan
753f46dffe arch/arm64: add support of systemreset 2022-12-07 21:17:39 +08:00
chao an
af149b44cd risc-v/backtrace: fix compile warning 
common/riscv_backtrace.c: In function 'up_backtrace':
common/riscv_backtrace.c:145:27: error: passing argument 1 of 'backtrace' from incompatible pointer type [-Werror=incompatible-pointer-types]
  145 |           ret = backtrace(g_intstackalloc,
      |                           ^~~~~~~~~~~~~~~
      |                           |
      |                           uint8_t * {aka unsigned char *}
common/riscv_backtrace.c:64:33: note: expected 'uintptr_t *' {aka 'unsigned int *'} but argument is of type 'uint8_t *' {aka 'unsigned char *'}
   64 | static int backtrace(uintptr_t *base, uintptr_t *limit,
      |                      ~~~~~~~~~~~^~~~
common/riscv_backtrace.c:146:43: error: passing argument 2 of 'backtrace' from incompatible pointer type [-Werror=incompatible-pointer-types]
  146 |                           g_intstackalloc + CONFIG_ARCH_INTERRUPTSTACK,
      |                                           ^
      |                                           |
      |                                           uint8_t * {aka unsigned char *}
common/riscv_backtrace.c:64:50: note: expected 'uintptr_t *' {aka 'unsigned int *'} but argument is of type 'uint8_t *' {aka 'unsigned char *'}
   64 | static int backtrace(uintptr_t *base, uintptr_t *limit,
      |                                       ~~~~~~~~~~~^~~~~

Regression by:
| commit 70290b6e38
| Author: Xiang Xiao <xiaoxiang@xiaomi.com>
| Date:   Tue Sep 20 02:38:54 2022 +0800
|
|     arch: Change the linker generated symbols from uint32_t to uint8_t *
|
|     and remove the duplicated declaration
|
|     Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: chao an <anchao@xiaomi.com>
 2022-12-07 19:13:09 +08:00
Gustavo Henrique Nihei
1ecaa4e672 xtensa/esp32s3: Configure the PMS peripheral for Protected Mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-12-07 03:07:45 +08:00
Gustavo Henrique Nihei
bfc40c74d0 xtensa/esp32s3: Add support for Protected Mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-12-07 03:07:45 +08:00
Lucas Saavedra Vaz
4320eed4a1 arch/xtensa/esp32: Optimize macros and ensure overwrite protection 2022-12-07 00:02:28 +08:00
Xiang Xiao
d6c8c269f5 arch/sim: Change usrsock_host_ prefix to host_usrsock_ 
to align with other similar function style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-12-06 13:12:21 +01:00
Xiang Xiao
79c8b7d3fd arch/sim: Change sim_host_ prefix to host_ 
to align with the other similar function style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-12-06 13:12:21 +01:00