This is a minimalistic SBI implementation for NuttX.
Provides a single service for now:
- Access to machine timer
Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.
Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
so the call gate does this from M-mode
The only supported (tested) target for now is MPFS.
ICMP's conn->dev is changing in icmp_sendmsg, when sending to different
address, or when error occurs (like NETDEV_DOWN). Then the poll callback
cannot be dropped from previous dev in free, because the dev is wrong.
So add dev to struct icmp_poll_s just like struct udp_poll_s.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
CortexR52 can have a optional FPU.
- VFPv3 with FP16
- Option 1: 16 x double-prevision registers - -mfpu=vfpv3-d16-fp16
- Option 1: 32 x double-prevision registers - -mfpu=vfpv3-fp16
This commit aims to provide a way to get the current applied defconfig on runtime by providing CONFIG_BASE_DEFCONFIG that is updated when the configure and build scripts are run.
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with nsh_smp on FVP
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This adds functionality to map pages dynamically into kernel virtual
memory. This allows implementing I/O remap for example, which is a useful
(future) feature.
Now, the first target is to support mapping user pages for the kernel.
Why? There are some userspace structures that might be needed when the
userspace process is not running. Semaphores are one such example. Signals
and the WDT timeout both need access to the user semaphore to work
properly. Even though for this only obtaining the kernel addressable
page pool virtual address is needed, for completeness a procedure is
provided to map several pages.
During initialization it isn't possible to use up_puts once it's
protected against concurrent access through a mutex lock. Instead,
using up_putc makes it similar to ESP32S2 and ESP32S3 and perfectly
fits for showprogress usage.
This commit reverts 19f269e54b and
substitutes the semaphore to a mutex, used as a locking mechanism
to avoid syslog messages being messed.
Considering SMP, threads running on different CPUs could call
syslog_default_write simultaneously. It then calls `up_nputs` that,
in most of the implementations, calls `up_putc` multiple times to
write to the serial. So, calling it at the same would cause syslog
messages to interfere with each other.
`up_nputs` and `up_putc` are low-level functions that could be used
during initialization and by the interrupt handler. Hence, it isn't
advisable to implement any locking mechanism on them. On the other
hand, syslog can also be used from the interrupt: if the interrupt
buffer is selected (`CONFIG_SYSLOG_INTBUFFER=y`), the syslog
messages will be flushed when we aren't serving an interrupt.
On the contrary, if it isn't set, it would call the registered
`sc_force` callback, which calls `syslog_default_putc` instead of
the lock-protected `syslog_default_write`.
in the initial impl, the regex is depends on ALLOW_MIT_COMPONENTS, and
if other modules want to use regex, also needs to depends on
ALLOW_MIT_COMPONENTS, which is ambiguity, so we provide a seperate
kconfig option for regex: LIBC_REGEX, which is depends on
ALLOW_MIT_COMPONENTS, but is enabled by default. Thus if
ALLOW_MIT_COMPONENTS is enabled, then the LIBC_REGEX is also enabled
either automatically, and this is more clear than controlled by
ALLOW_MIT_COMPONENTS option only.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
