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ad611e2cca
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5981 Commits

Author SHA1 Message Date
Gregory Nutt
ad611e2cca Merged in paulpatience/nuttx-arch (pull request #58) 
STM32 DAC: Fix DMA support for STM32F2xxx and STM32F4xxx
 2016-03-20 15:33:55 -06:00
Paul A. Patience
2f187f8714 STM32 DAC: Fix DMA support for STM32F2xxx and STM32F4xxx 2016-03-20 17:26:40 -04:00
Gregory Nutt
748edc0445 Fix a error in the previous commit 2016-03-20 14:23:45 -06:00
Gregory Nutt
e0249bd025 STM32L4: Fix incorrect and conflicting definitions for STM32L4_NGPIOS and STM32L4_NGPIO_PORTS. Now there is only STM32L4_NPORTS. 2016-03-20 14:12:07 -06:00
Gregory Nutt
f7d3b8147f Rename CONFIG_NET_MULTICAST to avoid name conflicts 2016-03-20 13:14:36 -06:00
Gregory Nutt
47b36e9de4 i.MX6: Fix uninitialized variable warning in GPIO logic 2016-03-19 13:59:50 -06:00
Gregory Nutt
2a15f73fd3 SAMV7 USB: Eliminate a warning 2016-03-17 17:43:29 -06:00
Gregory Nutt
0ff29023f1 SAMV7 USB: Fix a DMA related issue. When DMA completes with NBUSYBK greater than zero, need to way for NBUSYBK interrupt. 2016-03-17 17:43:29 -06:00
Gregory Nutt
bd846c2e72 All architectures: Register the schedule note driver if enabled 2016-03-17 17:00:59 -06:00
Gregory Nutt
82c58eb609 SIM: Register the schedule note driver if enabled 2016-03-17 14:43:29 -06:00
Gregory Nutt
8fbe5b6243 sim: Omit built-in scheduler imstrumentation if buffered instrumentation is selected. 2016-03-17 09:50:33 -06:00
Gregory Nutt
b1c09dc0c5 i.MX6: Hmm.. I think the i.MX6 Solo Lite has global and private timers. Note cleare from the reference manual 2016-03-16 10:54:55 -06:00
Gregory Nutt
e1ff2af690 All i.MX6 family members have GIC 390; SoloLite does not seem to have MPCore timers 2016-03-14 13:41:53 -06:00
Gregory Nutt
dcc93a7a44 Make it clear that GIC support is GICv2 2016-03-14 10:50:54 -06:00
Gregory Nutt
41b3af52b7 i.MX6: Revamp GIC initialization logic; add missing register bit definitions and initialization of GIC control register for secure cases 2016-03-13 10:12:45 -06:00
Gregory Nutt
411cf0ba1f SMP: Add per-CPU initialization logic 2016-03-13 07:16:26 -06:00
Gregory Nutt
2b2f157569 Forgot to add a file before last commit 2016-03-12 15:28:58 -06:00
Gregory Nutt
6288e381ee Conform to revised SMP interfaces. Improve i.MX6 SMP startup handshake. 2016-03-12 15:22:45 -06:00
Gregory Nutt
8ad1188fe5 i.MX6: Finish initial cut at all SMP support 2016-03-12 13:23:49 -06:00
Gregory Nutt
9addc363f5 i.MX6 no longer depends on EXPERIMENTAL 2016-03-12 11:46:53 -06:00
Gregory Nutt
11f3554153 i.MX6: Kconfg needs to autoselect ARCH_HAVE_TRUSTZONE 2016-03-12 11:40:27 -06:00
Gregory Nutt
cbe7321508 i.MX6: Finish GIC initialization 2016-03-12 11:38:16 -06:00
Gregory Nutt
08fa7a0c6b Rename CONFIG_SAMA5_HAVE_TRUSTZONE to CONFIG_ARCH_HAVE_TRUSTZONE; Eliminate CONFIG_SAMA5_SECURE; Add CONFIG_ARCH_TRUSTZONE_SECURE 2016-03-12 10:53:22 -06:00
Gregory Nutt
a1ee5ae6e5 EFM32 Serial: Fix typo in initializer. Noted by Pierre-noel Bouteville 2016-03-12 08:53:41 -06:00
Gregory Nutt
a74c19bbae SIM: Add TLS support to to the simulator 2016-03-11 14:03:27 -06:00
Gregory Nutt
4d484399a9 ARM: Remove some obsolete and incorrect conditional compilation 2016-03-11 12:42:58 -06:00
Michael Spahlinger
faa0c4f1ca SAMV7: MCAN: Correct typo in MCAN0 configuration 2016-03-11 12:30:57 -06:00
Gregory Nutt
4e07680554 TLS: Forgot to add a file before last commit 2016-03-11 12:30:04 -06:00
Gregory Nutt
87e7e135ba i.MX6: GIC decode and prioritization logic 2016-03-11 09:49:00 -06:00
Gregory Nutt
bc0fb5453a i.MX6: A little more GIC initialization logic 2016-03-11 09:00:49 -06:00
Gregory Nutt
1909dc8239 TLS: Move up_tls_info() to an inline function. Simplify TLS implementation. 2016-03-11 07:17:02 -06:00
Gregory Nutt
78e4ca2bc7 ARM: Partial implementation of TLS 2016-03-10 19:29:21 -06:00
Gregory Nutt
5445a1af83 Add a common ARM implementation of up_tls_info() 2016-03-10 18:10:17 -06:00
Gregory Nutt
a9b880a02b STM32L4: Fix a small error that prevent a clean compilation 2016-03-10 15:58:08 -06:00
Gregory Nutt
3d6519a223 Implement Cortex-A9 up_cpu_index() using the MPIDR register. Thanks Alan. 2016-03-10 14:02:58 -06:00
Sebastien Lorquet
1e5c4a83de Add stm32L4 I2C driver 2016-03-10 11:00:41 -06:00
Gregory Nutt
8e66043d7a Rename current_regs in STM32L4 for consistency with other platforms 2016-03-10 10:08:40 -06:00
Sebastien Lorquet
f4f03e6f02 Add port to the stm32L4 2016-03-10 09:59:16 -06:00
Gregory Nutt
a94febb551 MPCore: Fix missing header file inclusion; Add GIC-based implementations of up_enabable_irq(0 and up_disable_irq() 2016-03-10 08:37:34 -06:00
Gregory Nutt
5c75f83b55 ARMv7-A GIC: Add definitions for shared interrupt IDs 2016-03-10 07:13:40 -06:00
Gregory Nutt
4a8ac55c9d All SAM TWI: g_twiops should be both static and const 2016-03-09 18:11:55 -06:00
Gregory Nutt
400aead74a i.MX6: Add definitions for private processor interrupt IDs 2016-03-09 18:11:28 -06:00
Gregory Nutt
51be83aa3a ARM: Fix missing header file. Update comments in all *_irq.c files. 2016-03-09 15:08:58 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
7b0a696498 i.MX6: Add a system timer based on the i.MX6 GPT 2016-03-09 12:16:44 -06:00
Gregory Nutt
725e6878c4 i.MX6: Finish bit definitions in GPT header file 2016-03-09 09:31:36 -06:00
Gregory Nutt
80dce6dba1 i.MX6: Add incomplete GPT header file 2016-03-09 09:08:01 -06:00
Gregory Nutt
613786ff3d ARMv7-A: Add global timer header file 2016-03-09 08:36:22 -06:00
David Sidrane
a2052d006c Fix what I believe to be typos in SAMV7 timer 2016-03-08 17:26:01 -06:00
David Sidrane
72eef9f628 Ensure that CONFIG_ARMV7M_STACKCHECK works on the samv7 2016-03-08 17:22:07 -06:00