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chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default 
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp 
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
 2022-04-12 21:33:19 +08:00
anjiahao
c843cb8a52 libc/net:use strlcpy instead of strncpy 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 21:16:11 +08:00
anjiahao
c30705f5f0 libc/lib_glob:use strlcpy instead of memcpy 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 21:15:45 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break 
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
anjiahao
49cd445114 lib_localtime:fix unsigned compare with zero 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 17:10:14 +08:00
Lingao Meng
a56199c7dd sim: bt: Add specific bluetooth HCI number id 
Add option for attached the local bluetooth device use
specific bluetooth HCI number id.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
 2022-04-12 15:15:25 +08:00
YAMAMOTO Takashi
ade753488e .github/gcc.json: Fix space/tab inconsistency 2022-04-12 13:43:06 +08:00
SPRESENSE
64e5867a8b cxd56/spresense: Add callback mechanism to notice SDCard injection 
Add a mechanism to callback to an application to notice the SDCard
status is changed (inserted or ejected).
 2022-04-12 07:55:00 +09:00
SPRESENSE
81534df8a3 boards: cxd56xx: Add board function for scd41 sensor driver 
Add board function for SCD41 CO2, temperature and humidity sensor driver.
 2022-04-12 07:55:00 +09:00
SPRESENSE
771bd8ca17 board/spresense: Add pin selection of ILI934x 
Add Kconfig choice for selecting RST and DC pins on ILI934x LCD.
 2022-04-12 07:55:00 +09:00
SPRESENSE
22d2ef0bf4 boards: cxd56xx: Make board_late_initialize a weak function 
Add a weak_function to the board_late_initialize function so that
it can be replaced by another file, such as a user application.
 2022-04-12 07:55:00 +09:00
SPRESENSE
c2e45444ff boards: cxd56xx: Fix an issue i2c tool not working 
It caused i2c tool not to work due to i2c uninitializing processing.
Since this process is not necessary in the normal case, we will
move it to the error case.
 2022-04-12 07:55:00 +09:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver 
Add critical section to scu one-shot sequencer.
 2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning 
Add necessary include header named debug.h for using ferr and
finfo.
 2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20585
 2022-04-12 07:55:00 +09:00
chao.an
a594a5d7a8 sched/init: drivers_initialize() should be late than up_initialize() 
up_initialize
|
 ->up_serialinit
   |
    ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

drivers_initialize
|
 ->syslog_console_init
   |
    ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 07:51:34 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00
anjiahao
bb6279fe60 libc/lib_localtime:fix deadcode 
isdst always is false

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 01:51:29 +08:00
Petro Karashchenko
ea5ffac7d1 drivers/syslog: update description if Kconfig 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-11 23:36:39 +08:00
SPRESENSE
46a92aeebb graphics/nxterm: Avoid accessing freed memory 
Fix accessing freed priv data.
 2022-04-11 20:50:09 +08:00
songlinzhang
8dd5d0d510 netdb/lib_dnsaddserver.c: Do not insert the duplicate DNS address 
Signed-off-by: songlinzhang <songlinzhang@xiaomi.com>
 2022-04-11 20:31:15 +08:00
YAMAMOTO Takashi
c9f3b3a7f1 littelfs: deal with block devices w/o ioctl 
Note: Some block devices has ioctl == NULL. eg. drivers/loop
 2022-04-11 13:38:26 +03:00
SPRESENSE
9cd53d714e drivers/sensors/sgp30: Fix redundant parameter check 
Fix redundant conditions.
 2022-04-11 13:29:35 +03:00
SPRESENSE
3787a362bf drivers/sensors/scd30: Fix invalid parameter check 
Fix invalid parameter check and redundant conditions.
 2022-04-11 13:29:35 +03:00
SPRESENSE
bf332cf888 drivers/sensors: Add new driver for scd41 sensor module 
Add Sensirion's SCD41 CO2, temperature and humidity sensor driver.
 2022-04-11 13:29:35 +03:00
chao.an
609e949ab0 sched/note: include-able from C++ files 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-11 16:30:27 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-11 10:59:18 +03:00
wangbowen6
d4978bfba4 mm_initialize: malloc() return aligend pointer. 
malloc() should return aligned (with MM_MIN_CHUNK) pointer, but
pr #5906 destroy that, this pr find a better method to solve
these questions.

Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
and
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-11 12:46:17 +08:00
wangbowen6
1a4ccd2d70 Revert "mm_heap: heapsize align with MM_MIN_CHUNK." 
This reverts commit 69e69740b5.
 2022-04-11 12:46:17 +08:00
okayserh
218cbb470a Fixed source code format errors. 2022-04-10 19:12:10 -03:00
okayserh
56f0d72465 Minor fix, function name was wm8994_setvolume instead of 
wm8904_setvolume.
 2022-04-10 19:12:10 -03:00
okayserh
eb3e8175de Fixes some issues with the implementation of the balance 
functionality. In function "wm8904_hw_reset" the priv->balance
is initialized with b16HALF, indicating a range from
0 to b16ONE. In function "wm8904_setvolume" the assumed
range for priv->balance is between 0 and 1000. The changes
now make this consistent for 0 to b16ONE-1. Furthermore,
in wm8904_configure the change of balance was not implemented.
 2022-04-10 19:12:10 -03:00
Xiang Xiao
1a6ee1b908 audio: Don't register audio device if name isn't given in audio_comp_initialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-10 15:41:14 -03:00
zhangyuebin
f3d20abe07 audio: Return audio_lowerhalf_s pointer instead error code in audio_comp_initialize 2022-04-10 15:41:14 -03:00
nietingting
dd70d29d4e tools/mkdeps: Extend MAX_SHQUOTE to 3072 
Signed-off-by: nietingting <nietingting@xiaomi.com>
 2022-04-10 09:55:14 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception 
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core 
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
liuhaitao
c4e2d88e6b Make top Make.defs symlink to board Make.defs instead 
Symlink to board Make.defs for top Make.defs, so top Make.defs
syncs in realtime.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
 2022-04-10 01:28:27 +02:00
Xiang Xiao
0f82eccc4f .github/workflows/check.yml: Enable Change-ID check explicitly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-09 22:06:54 +02:00