Gustavo Henrique Nihei
b49ee3d4ed
xtensa/esp32s3: Add support for Main System Watchdog Timers
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Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 02:13:00 +08:00
Gustavo Henrique Nihei
a5024a707d
xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
83f3ba6d22
xtensa/esp32s3: Add support for Timer Groups 0 and 1
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 00:13:34 +08:00
zhuyanlin
fc9791c269
xtensa:esp32s3: setup software interrupt as swi interrupt.
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Enable and setup software interrupt.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
Abdelatif Guettouche
ab18b7b3d3
esp32xx_irq.c: Fix CPU interrupt documentation to remove the MAC
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interrupt from the internal interrupt table.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Xiang Xiao
4c167b0729
Correct the code alignment
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Gustavo Henrique Nihei
b0d24f53c4
xtensa: Add initial support for ESP32-S3
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Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
