Commit Graph

1397 Commits

Author SHA1 Message Date
SPRESENSE
f3fabc5d32 Revert "make/archive: Use the full path name when matching or storing names in the archive"
This reverts commit 563125fde3.
2023-10-27 22:26:18 +08:00
xuxin19
9112b9e4c0 cmake:add zifencei extension in compile options
this fixes the error opcode `fence.i` by cmake compilation

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-10-26 21:01:46 +08:00
xuxin19
e3003f691b cmake:init RISC-V cmake qemu-rv build
cmake currently does not support non-FlatBuild,
need disable ELF and LOADABLE when compiling other defconfigs

```
 cmake -B build -DBOARD_CONFIG=rv-virt/smp64 -GNinja # for rv32:rv-virt/smp
 cmake --build build -t menuconfig
 cmake --build build
 qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 -bios none -kernel nuttx -nographic
```

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-10-26 21:01:46 +08:00
Tiago Medicci Serrano
a2be27ef7d espressif: Update esp-hal-3rdparty version
This version includes a bugfix for the NULL definition.
2023-10-26 20:02:13 +08:00
Stuart Ianna
5fa1819492 arch/risc-v/litex/litex-emac: Add support for phy interrupts.
Add support for PHY interrupts in the architecture layer of the Litex emac driver. Boards need to add handling for interrupt lines, if supported.
2023-10-26 09:02:23 +08:00
chao an
3cadf6642a kernel: replace all usleep to nxsig_usleep in kernel space
syscall cannot be called from kernel space

Signed-off-by: chao an <anchao@xiaomi.com>
2023-10-25 15:46:03 +08:00
Stuart Ianna
ee84ea3875 arch/risc-v/litex/litex_gpio: Fix ISR dispatch when using higher GPIO indexes.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.

Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
2023-10-25 15:42:25 +08:00
Stuart Ianna
ac5800386c arch/risc-v/litex/litex_emac: Add support for KSZ8061 ethernet PHY.
Adds support for using the microchip KSZ8061 ethernet PHY instead of the default DP83848C.
2023-10-25 13:33:03 +08:00
Ville Juven
9c725c4903 arch/risc-v: Simplify pmp_check_region_attrs sanity-checks
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
           and size must be power-of-two aligned with base

This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
2023-10-23 13:10:59 -03:00
Ville Juven
8e6b448f47 arch/risc-v: Remove unnecessary PMP kconfig options
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
2023-10-23 13:10:59 -03:00
Ville Juven
0e75e53cc8 mpfs_head.S: Simplify clearing PMP
Initially clear PMP for all harts, this fixes random warm reset issues.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2023-10-17 20:13:09 +08:00
Ville Juven
3f878d8100 mpfs_ethernet.c: Release tx descriptor and rx buffer properly
Instead of releasing rx descriptor twice and tx buffer twice.
2023-10-16 21:54:31 +08:00
Ville Juven
ee9e41f2dd mpfs_ethernet.c: Fix possible NULL de-reference
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
2023-10-16 21:54:31 +08:00
Ville Juven
64b6ac3d87 mpfs/mpfs_entrypoints.c: Fix potential R_RISCV_JAL linker error
Change bgtz t0, mpfs_opensbi_prepare_hart to tail-call to ensure there
will be no link time error due to the jump offset being too large.
2023-10-16 21:52:01 +08:00
TaiJuWu
1989749850 cpu_pause.c: fix typo
Signed-off-by: TaiJuWu <tjwu1217@gmail.com>
2023-10-14 00:26:31 -04:00
hujun5
061be5f18e refine: move BIT Macro to nuttx/bits.h
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 14:52:56 +08:00
Ville Juven
d199264dca kmm_map: Fix incorrect function name field 2023-10-09 18:59:43 +03:00
Ville Juven
3e8575c39e riscv-v/pgalloc.h: Return kernel vaddr for kernel RAM paddr
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
2023-10-09 18:59:25 +03:00
Xiang Xiao
dfa0283d83 spinlock: Rename spin_islocked to spin_is_locked
align with Linux naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-10-06 20:03:19 -04:00
Ville Juven
7901ed0fe3 riscv_addrenv_utils.c: Determine page table flags by type of vaddr
Use kernel page table flags if the mapped virtual address is in kernel
space.
2023-10-05 20:38:35 +08:00
Ville Juven
8c6be8e1f3 riscv/addrenv: Fix the user VMA end address
The end address was off by 1, making it overflow to 0 (u32 value).
2023-09-29 22:34:40 +08:00
Xiang Xiao
cb11747f36 arch: add use_data to g_tcbinfo
to avoid compiler/linker remove it from the final image

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-29 08:00:18 +03:00
Ville Juven
7b18f5eb6f risc-v/riscv_addrenv.c: Fix bug where SHM area page tables are not freed
The SHM physically backed memory does not belong to the user process,
but the page table containing the mapping does -> delete the page table
memory regardless.
2023-09-28 22:17:55 +08:00
Ville Juven
2cd1fd1145 risc-v/pgalloc.h: Add SHM area to riscv_uservaddr query
If the vaddr resides within the user's SHM, it is a user memory mapping.
2023-09-28 22:17:55 +08:00
Ville Juven
9be93addea mpfs/mpfs_corespi: Several speed optimizations to the FPGA driver
This is a collection of tweaks / optimizations to the driver to limit
CPU usage as well as interrupt processing times.

The changes are as follows:
- setfrequency is now no-op if the frequency does not change. Accessing
  MPFS_SPI_CONTROL requires synchronization to the FIC domain, which
  takes unnecessary time if nothing changes
- load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are
  only tested once (instead of for every word written in loop).
- Disable the RX interrupt only once (again, FIC domain access is slow)
- In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the
  whole RX FIFO, instead of trying to read it byte-by-byte
2023-09-28 09:36:07 +08:00
makejian
cb3abc48d7 crypto/cryptodev: expansion hash operation
(1) remove size restriction for single hash operation
(2) support hash operation to update uint32_t data
Signed-off-by: makejian <makejian@xiaomi.com>
2023-09-24 03:49:33 +08:00
wanggang26
7f5e6bd383 hostfs: mask bit fields of not support
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2023-09-23 05:28:57 +09:00
Eero Nurkkala
8f5a6930e8 riscv/riscv_pmp.c: fix broken TOR checks
PMPCFG_A_TOR region may have zero size. The pmp configuration
currently fails for zero-sized TOR. This patch bypasses such a
restriction.

Also replace log2ceil with LOG2_CEIL from lib/math32.h.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-09-21 01:10:49 +08:00
ThomasNS
a2c806027f fix led panic feature 2023-09-21 00:35:12 +08:00
Huang Qi
ac5e99d330 espressif: Force cast param in libc stubs
Fix:
```
chip/esp_libc_stubs.c: In function '__retarget_lock_init':
Error: chip/esp_libc_stubs.c:246:14: error: passing argument 1 of '_lock_init' from incompatible pointer type [-Werror=incompatible-pointer-types]
  246 |   _lock_init(lock);
      |              ^~~~
      |              |
      |              struct __lock **
chip/esp_libc_stubs.c:181:26: note: expected 'int *' but argument is of type 'struct __lock **'
  181 | void _lock_init(_lock_t *lock)
      |                          ^
chip/esp_libc_stubs.c: In function '__retarget_lock_init_recursive':
Error: chip/esp_libc_stubs.c:251:24: error: passing argument 1 of '_lock_init_recursive' from incompatible pointer type [-Werror=incompatible-pointer-types]
  251 |   _lock_init_recursive(lock);
      |                        ^~~~
      |                        |
      |                        struct __lock **
chip/esp_libc_stubs.c:187:36: note: expected 'int *' but argument is of type 'struct __lock **'
  187 | void _lock_init_recursive(_lock_t *lock)
      |                                    ^
chip/esp_libc_stubs.c: In function '__retarget_lock_close':
Error: chip/esp_libc_stubs.c:256:15: error: passing argument 1 of '_lock_close' from incompatible pointer type [-Werror=incompatible-pointer-types]
  256 |   _lock_close(&lock);
      |               ^~~~~
      |               |
      |               struct __lock **
chip/esp_libc_stubs.c:193:27: note: expected 'int *' but argument is of type 'struct __lock **'
  193 | void _lock_close(_lock_t *lock)
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-09-20 17:04:56 +08:00
Huang Qi
74e59feaaa rv32m1: Fix compile error
Follow other risc-v based chips, and fix:
```
chip/rv32m1_irq.c: In function 'up_irqinitialize':
Error: chip/rv32m1_irq.c:98:3: error: array subscript -2048 is outside array bounds of 'uint8_t[2147483647]' {aka 'unsigned char[2147483647]'} [-Werror=array-bounds]
   98 |   riscv_stack_color(g_intstacktop - intstack_size, intstack_size);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_internal.h:40,
                 from chip/rv32m1_irq.c:36:
/github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_common_memorymap.h:72:16: note: at offset -2048 into object 'g_intstacktop' of size [0, 2147483647]
   72 | EXTERN uint8_t g_intstacktop[];   /* Initial top of interrupt stack */
      |                ^~~~~~~~~~~~~
cc1: all warnings being treated as errors
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-09-20 17:04:56 +08:00
chao an
5026a96cfa nxstyle: cleanup UTF-8 Unicode to ASCII
Signed-off-by: chao an <anchao@xiaomi.com>
2023-09-18 11:54:17 -04:00
Huang Qi
43610f75f1 tools: Use GCC 13.2 from xPack for risc-v 2023-09-18 21:25:13 +08:00
Ville Juven
1532ccbd59 risc-v/mpfs: Add DMA buffer allocator for eMMC access
The MPFS eMMC DMA has some requirements that are only fulfilled by
enabling separate DMA access buffers (FAT DMA buffers) and by forcing
indirect access to the media via FAT_FORCE_INDIRECT.

Why? Direct access to user buffers violates two things:
- Buffer alignment is not ensured
- Buffers are user memory (problematic in BUILD_KERNEL)
2023-09-18 21:03:36 +08:00
Xiang Xiao
8dbe86084e Remove FAR from source code under 32bit arch and board
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-16 19:12:13 +03:00
Petro Karashchenko
017ccca5d6 arch/risc-v/esp32c6: fix compilation of esp32c6 serial driver
The commit fix regression introduced by c56aa7b527

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 18:29:59 +08:00
Petro Karashchenko
c56aa7b527 esp32: use ESP32 specific macro for register values extraction
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
Petro Karashchenko
dbc37a0165 nuttx: fix nxstyle issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
Petro Karashchenko
816cb3cfaf style: fix multiple style issues and remove unused
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
simbit18
b3973496cd Fix Kconfig style
Remove spaces from Kconfig
Add comments
2023-09-13 21:39:49 +08:00
Jukka Laitinen
bd52ae1ad9 arch/risc-v/src/mpfs/mpfs_i2c.c: Clean up using priv->status and STOP interrupts
- There are occasional extra STOPs being sent due to an IP bug when using an
  FPGA based I2C. Add a flag "inflight" to mask out extra STOP interrupts when
  using the FPGA based implementation
- There are no MPFS_I2C_ST_STOP_SENT irq's "initally". It is just already
  either success or still in progress

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-12 22:11:24 +08:00
Jukka Laitinen
a6388b8843 arch/risc-v/src/mpfs: Add ksz9477 initialization
This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-08 22:34:27 +08:00
Jukka Laitinen
b750f94896 arch/risc-v/src/mpfs: Generate an unique locally administrated MAC address
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-07 00:53:00 +08:00
Jari Nippula
ef18d2b599 arch/riscv/src/mpfs/mpfs_ethernet.c: discard err rxframe in int work
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.

In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
2023-09-07 00:53:00 +08:00
Xu Xingliang
a2df576ecf kasan: add option to disable read/write checks
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2023-09-07 00:41:43 +08:00
Eero Nurkkala
0152b031a4 risc-v/mpfs: enhance rpmsg throughput
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.

Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.

Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.

In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-09-06 14:32:11 +08:00
Seppo Hirvela
67ad63c7a4 risc-v/mpfs: ihc: fix to work with the latest NuttX OpenAMP version 2023-09-06 14:32:11 +08:00
Jani Paalijarvi
a1aebb7a64 risc-v/mpfs: ihc: Minor fixes
Remove unnecessary VQID shifting (16 -> 0).
Give an error if RPTUN init fails.
2023-09-06 14:32:11 +08:00
Jani Paalijarvi
cc5e8222b3 risc-v/mpfs: ihc: Increase RPMSG buffer size
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2023-09-06 14:32:11 +08:00
Jani Paalijarvi
3bd4bd6196 risc-v/mpfs: ihc: Make Vring addresses configurable 2023-09-06 14:32:11 +08:00