Commit Graph

53701 Commits

Author SHA1 Message Date
guoshichao
d76218e817 greenhills: fix the moblib asm compile error
CC:  assert/lib_assert.c [asarm] (error #2179) modlib/modlib_globals.S 61: unexpected token type (char) encountered; expected type (identifier)
  .size \ globalNames , . - \ globalNames
--------^

[asarm] (error #2179) modlib/modlib_globals.S 67: unexpected token type (char) encountered; expected type (identifier)
  .size \ nglobals , . - \ nglobals
--------^

[asarm] (error #2179) modlib/modlib_globals.S 72: unexpected token type (char) encountered; expected type (identifier)
  .size \ global_table , . - \ global_table
--------^

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-11 14:28:12 -03:00
guoshichao
ed9d57b501 greenhills: fix the arch_setjmp.S build error
CC:  bch/bchlib_read.c [asarm] (error #2067) machine/arm/gnu/arch_setjmp.S 34: unknown instruction
  .syntax unified
--^

[asarm] (error #2230) machine/arm/gnu/arch_setjmp.S 62: bad directive
  .type setjmp , function
-----------------^

[asarm] (error) errors during processing

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-11 14:28:12 -03:00
guoshichao
693e869404 arm-m/barrier: fix green hills build ARM_ISB error
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"

So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:

CC:  common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
  isb 15
------^

[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
  isb 15
------^

[asarm] (error) errors during processing

According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.

In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-11 14:28:12 -03:00
fangxinyong
6da525704d toolchain/ghs: fix the inline assembly code register alloc compile error
The following are the compile error that reported
by GreenHills compiler:

"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
          cannot allocate "reg0" to specified caller-saved register

 "/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
          cannot allocate "reg1" to specified caller-saved register

Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:

CC:  proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
                 from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
                 from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
    inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
  297 |   __asm__ __volatile__
      |   ^~~~~~~

2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
2024-08-11 14:28:12 -03:00
yanghuatao
5bb805b229 toolchain/ghs: Fix green hills toolchain build Vela asarm errors
common/gnu/fork.S 29: unknown instruction
  .syntax unified
--^
[asarm] (error #2230) common/gnu/fork.S 81: bad directive
  .type up_fork , function
------------------^
[asarm] (error #2067) armv7-m/arm_saveusercontext.S 31: unknown instruction
  .syntax unified
--^

[asarm] (error #2230) armv7-m/arm_saveusercontext.S 55: bad directive
  .type up_saveusercontext , % function
--^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 65: not within valid register range
  str r12 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 4 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 66: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 5 ) ) ]
------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 67: not within valid register range
  str r14 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 6 ) ) ]
------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 72: expected a register
  str r1 , [ r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 7 ) ) ]
------------------^

[asarm] (error #2004) armv7-m/arm_saveusercontext.S 75: not within valid register range
  add r1 , r0 , ( 4 * ( ( ( 12 ) + ( 16 ) ) + 8 ) )
-----------^

[asarm] (error #2071) armv7-m/arm_saveusercontext.S 89: bad parameter
  stmia r0 ! , { r2 - r11 }
--------^

[asarm] (error #2014) armv7-m/arm_saveusercontext.S 93: expected a register
  mov r1 , - 1
-----------^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
yanghuatao
3e171489bd toolchain/ghs: Fix green hills toolchain build Vela link error
[elxr] (error #412) unresolved symbols:
 __builtin_frame_address     from libarch.a(arm_checkstack.o)

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:27:02 -03:00
Yanfeng Liu
47b0414eab arch/riscv: add cluster local hartid
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.

This allows us to get local ids by offsetting mhartids with a
base value.

Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 00:10:13 +08:00
anjiahao
029411f00c arm:Select ram vector on armv6m
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-08-12 00:09:56 +08:00
Yanfeng Liu
76b58e4af0 board/lm3s6965-ek: restore 128K kflash
This reverts both 2afdcfb6a6 and 0a0af89de9 to restore the 128K kflash
design as the implementation depends on that to work, checked with:

```
$ qemu-system-arm -M lm3s6965evb -nographic -device \
    loader,file=nuttx.bin,addr=0x0 -device \
    loader,file=nuttx_user.bin,addr=0x2000
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-11 19:00:18 +08:00
Nicolas Gariepy
af78534df9 fix stm32wl5_rcc.h: Add the missing argument to RCC_PLLCFG_PLLP define. 2024-08-11 03:10:20 +08:00
Alan C. Assis
fe10abe4a0 arm/stm32f103-minimum: Use common board MFRC522 2024-08-11 03:09:40 +08:00
Rodrigo Sim
208b8e084f arm/stm32f401rc-rs485: Add support to BMP280 sensor
Signed-off-by: Rodrigo Sim <rcsim10@gmail.com>
2024-08-11 03:09:14 +08:00
Daniel Jasinski
d77ef098c6 build: set CMake policy to allow FetchContent_Populate
FetchContent_Populate is depracated starting from CMake
3.30. Setting this policy to OLD allows clean CMake builds
for configurations that rely on CMake fetch content feature.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-11 03:03:57 +08:00
Alan C. Assis
7e0db94063 arm/lm3s6965-ek: Disable NTPC for lm3s6965 to fix maximum flash space reached 2024-08-10 19:26:32 +08:00
Yanfeng Liu
0a0af89de9 board/lm3s6965-ek: fix memory.ld for PROTECTED
The uflash origin should equal to kflash size, this completes the
fix to unblock CI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-10 19:21:35 +08:00
chenwen@espressif.com
cde0de00fe xtensa/esp32s3: Update the rtc code to fix system blocking issue
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
      but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
   2. Corresponding issue link: 89cc9084ab

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-08-09 12:49:34 -03:00
Yanfeng Liu
83932d115b boards/rv-virt: unify rv32 config names
This renames a few RV32 configs to follow the convention that names w/o
numbers are for RV32, so that to be in line with majority RV32 configs.

As a result, we have:  `nsh` vs `nsh64`, `knsh` vs `knsh64`, `pnsh`
vs `pnsh64`,`flats` vs `flats64`, `nsbi` vs `nsbi64`, `libcxx` vs
`libcxx64` etc. This helps us pick the right config name w/o checking
file contents.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:44:40 +08:00
Yanfeng Liu
2afdcfb6a6 boards/lm3s6965-ek: adjust memory.ld to unblock CI
This adjusts memory.ld to unblock CI issue: `nuttx_user.elf
section '.text' will not fit in region 'uflash'`

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu
46f4a24d59 riscv/qemu: add CMake for PROTECTED
This adds CMake support for PROTECTED build mode on rv-virt target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu
34a30e577e riscv/qemu: add CMake for NuttSBI
This allows building NuttSBI based kernel image with CMake so that
to support out-of-tree building.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
chao an
6c97a8f468 sim/login: remove login restrictions to improve the experience for green hands
Most developers start learning Nuttx from sim/nsh, but the login experience is very bad,
they don't know where to get the username and password, this commit will remove the
limitation of sim/nsh login, and add sim/login configuration to ensure the feature of
NSH_CONSOLE_LOGIN is verified.

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-09 11:34:38 -03:00
Saurav Pal
0be6dfb552 fs/mnemofs: Refactor path logic, direntry size bug fix, open free bug fix
Refactoring path logic to prevent logic flaws, direntry size bug fix to allow proper direntry traversal, open free bug fix to prevent memory leak after close.

Signed-off-by: Saurav Pal <resyfer.dev@gmail.com>
2024-08-09 09:00:17 +02:00
Nonpawit Ekburanawat
01bac59cb7 Add STM32H745I-DISCO Per Core Support
- New defconfig for nsh CM4 and CM7
- New linker script for cm4
- Update linker script to include shared memory and condition for flash size
- Update Make and CMake file to compile according to core
- Added UART7 pin by default for CM4 serial output
- Changed userled configuration to fix error

Signed-off-by: Nonpawit Ekburanawat <nonpawit.ek@gmail.com>
2024-08-09 01:58:51 +08:00
Yanfeng Liu
bba82bea89 build/cmake: allow gcc-riscv64-unknown-elf for PROTECTED
This allows using Ubuntu stock gcc-riscv64-unknown-elf 10.2
toolchain for PROTECTED build with cmake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 01:58:36 +08:00
Yanfeng Liu
01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
nuttxs
2af8a886ab arch/xtensa/esp32: Replace nxsig_usleep() with up_udelay() to
avoid context switching, and the actual time difference caused
by the setting of TICK in nxsig_usleep() is quite large.
2024-08-08 20:01:46 +08:00
rongyichang
bb29c39d50 drivers/touchscreen: add grab for touchscreen
Providing the capability for applications to exclusively
handle touch events

Signed-off-by: rongyichang <rongyichang@xiaomi.com>
2024-08-08 18:30:32 +08:00
chao an
9cc25523b1 spinlock: add support of spin_trylock_irqsave()
trylock spinlock in critical section:

bool spin_trylock_irqsave(FAR volatile spinlock_t *lock, irqstate_t flags);
bool spin_trylock_irqsave_wo_note(FAR volatile spinlock_t *lock, irqstate_t flags);

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-08 18:26:59 +08:00
Shoukui Zhang
a3b94383ed tmpfs: write end of file if open flag with O_APPEND
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-08 17:19:42 +08:00
Shoukui Zhang
3f3ad34f42 Fix greater-than-or-equal-to-zero issue
unsigned_compare: This greater-than-or-equal-to-zero comparison without a signed value is always true. conn->lc_crefs >= 0

Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-08 17:19:42 +08:00
Lup Yuen Lee
3862b71728 risc-v/qemu-rv: Add Build Config for leds64_rust
This PR adds a new Build Config `rv-virt:leds64_rust` that builds the Rust App `leds_rust` for QEMU RISC-V 64-bit. The build requires the [Rust Target `riscv64gc-unknown-none-elf`](https://github.com/apache/nuttx/pull/12858):

```bash
rustup target add riscv64gc-unknown-none-elf
```

New Files:

`boards/risc-v/qemu-rv/rv-virt/configs/leds64_rust/defconfig`: Add new Build Config `rv-virt:leds64_rust`

Updated Docs:

`applications/examples/leds_rust/index.rst`: Add `leds_rust` example app

`platforms/risc-v/qemu-rv/boards/rv-virt/index.rst`: Add `rv-virt:leds64_rust` config
2024-08-08 12:19:25 +08:00
Daniel Jasinski
8399a780d8 build: Fix Toolchain.cmake for CONFIG_SIM_ASAN enabled
This commit adds missing add_link_options to specify sanitizers
also during linking stage.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-08 09:44:47 +08:00
Yanfeng Liu
77cfbf8914 riscv/fork: fix gp register handling
This fixes the handling of gp register in fork.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Yanfeng Liu
3f021d5429 riscv/fork: fix fp/s0 field position
The fp/s0 field position shall be in line with the macro
FORK_FP_OFFSET/FORK_S0_OFFSET.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
zhangshoukui
5df3f5d4f7 Added the documentation about the iic slave driver
Signed-off-by: zhangshoukui <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
75fa94af02 i2c_slave: add poll waiters array
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
f94160095e Adapt i2c slave callback interface for rp2040 and s32k11x
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
4e6f3e9360 I2c slave: Add POLLOUT event for notifie slave write success
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
2093038315 add setup and shutdown for i2c master and slave
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
1ea19e7c54 fix i2c slave register failed
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
f4a234613e Add I2C Slave driver
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
6114c0b948 i2c: Remove useless restrictions
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
2bf13ffbb0 spi: Optimize access to private data
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
a6cea0d82e Restriction declaration spi_slave_unlink function
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Shoukui Zhang
9ffac12465 spi: Remove useless restrictions
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Lup Yuen Lee
52583fc17e tools/ci: Add Rust Target for QEMU RISC-V 64-bit
This PR updates the Docker Image for NuttX CI, so that it builds Rust Apps correctly for QEMU RISC-V 64-bit. We add the Rust Target for `riscv64gc-unknown-none-elf` to the Docker Image.

In the next PR, we will call the Updated Docker Image to [compile the Rust App `leds_rust`](https://github.com/apache/nuttx/pull/12852), at every run of NuttX CI. This will validate whether Rust Apps are built correctly for QEMU RISC-V 64-bit.

Modified Files:

`tools/ci/docker/linux/Dockerfile`: Add Rust Target `riscv64gc-unknown-none-elf` for Docker CI

`tools/ci/platforms/ubuntu.sh`: Same as above, but for Ubuntu CI

`tools/ci/platforms/msys2.sh`: Same as above, but for MSYS2 CI
2024-08-07 19:59:56 +08:00
zouboan
d759611e90 Documentation/platforms:add documentation for Zynq MPSoC and ZCU111
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
2024-08-07 16:21:51 +08:00
YAMAMOTO Takashi
d9c90eef13 esp32s3-devkit/toywasm: enable ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK 2024-08-07 15:59:41 +08:00
Lup Yuen Lee
788f91c677 tools/[Rust|D]: Fix the Rust and D Builds for QEMU RISC-V
This PR fixes the build for Rust Apps and D Apps on QEMU RISC-V. Previously the Rust Build selected the [incorrect Rust Target riscv64i-unknown-none-elf](https://lupyuen.github.io/articles/rust5#rust-target-is-incorrect). Now the Rust Build selects the correct Rust Target: riscv64gc-unknown-none-elf.

This PR also fixes the 32-bit RISC-V Target for D Apps. D Targets ("riscv32") are named differently from Rust Targets ("riscv32gc"), this PR restores the correct Target Names.

Note that Rust Apps won't build correctly for QEMU RISC-V 32-bit. This requires a [Rust Custom Target for riscv32gc](https://lupyuen.github.io/articles/rust4#custom-target-for-rust), which will make the NuttX Makefiles much more complicated.

Also note that `hello_d` won't build correctly for 64-bit `rv-virt:nsh64`. To date, NuttX has never supported 64-bit RISC-V for D Apps.

Modified Files:

`tools/Rust.defs`: Rename the RISC-V ISA `imafdc` to `gc` for Rust Targets

`tools/D.defs`: Exclude the RISC-V ISA for D Targets
2024-08-07 10:03:43 +08:00