4c601faf6f
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
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|---|---|---|
| .. | ||
| adc | ||
| highpri | ||
| include | ||
| nsh | ||
| scripts | ||
| spwm1 | ||
| spwm2 | ||
| src | ||
| Kconfig | ||
| README.txt | ||
Nucleo-64 Boards
================
The Nucleo-F334R8 is a member of the Nucleo-64 board family. The Nucleo-64
is a standard board for use with several STM32 parts in the LQFP64 package.
Variants include
Order code Targeted STM32
------------- --------------
NUCLEO-F030R8 STM32F030R8T6
NUCLEO-F070RB STM32F070RBT6
NUCLEO-F072RB STM32F072RBT6
NUCLEO-F091RC STM32F091RCT6
NUCLEO-F103RB STM32F103RBT6
NUCLEO-F302R8 STM32F302R8T6
NUCLEO-F303RE STM32F303RET6
NUCLEO-F334R8 STM32F334R8T6
NUCLEO-F401RE STM32F401RET6
NUCLEO-F410RB STM32F410RBT6
NUCLEO-F411RE STM32F411RET6
NUCLEO-F446RE STM32F446RET6
NUCLEO-L053R8 STM32L053R8T6
NUCLEO-L073RZ STM32L073RZT6
NUCLEO-L152RE STM32L152RET6
NUCLEO-L452RE STM32L452RET6
NUCLEO-L476RG STM32L476RGT6
Configurations
==============
nsh:
----
Configures the NuttShell (nsh) located at apps/examples/nsh.
adc:
----
Configures the ADC example located at apps/examples/adc.
highpri:
--------
Configures the high priority interrupts example (ADC + PWM)
spwm1 and spwm2:
----------------
Configures the sinusoidal PWM (SPWM) example which presents a simple use case
of the STM32 PWM lower-half driver without generic upper-half PWM logic.
There are two variants of this example, where functionality is achieved with
different periperals:
- spwm1 uses HRTIM to generate PWM and change waveform samples
- spwm2 uses TIM1 to generate PWM and TIM6 to change waveform samples
At the moment, the waveform parameters are hardcoded, but it should be easy to
modify this example and make it more functional.