nuttx/arch/arm/src/armv7-m
2016-04-10 09:11:50 -06:00
..
gnu ARMv7-M: Add toolchain option to select the IAR tools. Move ARMv7-M assembly language into a gnu/ subdirectory. Makefile selects iar/ or gnu/ directory based upon tool configuration 2016-04-02 07:53:52 -06:00
iar Oops: Forgot to add file in previous commit 2016-04-10 09:11:50 -06:00
arch_clean_dcache_all.c SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this 2015-03-29 13:09:22 -06:00
arch_clean_dcache.c SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this 2015-03-29 13:09:22 -06:00
arch_disable_dcache.c Break ARMv7E-M cache operations into separate files; Finish the unimplemented cache operations 2015-03-17 08:48:41 -06:00
arch_enable_dcache.c Costmetic fixes to C coding style 2015-10-05 17:13:53 -06:00
arch_flush_dcache_all.c SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this 2015-03-29 13:09:22 -06:00
arch_flush_dcache.c SAMV7/Cortex-M7: Add support for write through D-Cache. SAMV7 Ethernet look like it needs this 2015-03-29 13:09:22 -06:00
arch_invalidate_dcache_all.c Break ARMv7E-M cache operations into separate files; Finish the unimplemented cache operations 2015-03-17 08:48:41 -06:00
arch_invalidate_dcache.c Break ARMv7E-M cache operations into separate files; Finish the unimplemented cache operations 2015-03-17 08:48:41 -06:00
cache.h SAMV7 QSPI: When QSPI is enabled, make the QSPI memory strongly ordered 2015-11-06 12:10:15 -06:00
dwt.h Add ARMv7-M DWT and TPI register definitions 2014-10-21 16:46:26 -06:00
etm.h Add optional timestamp to syslog output. From pn_bouteville@yahoo.fr 2014-11-01 09:17:34 -06:00
exc_return.h Add new common lazy FPU state saving option for ARMv7-M. Not yet verified 2015-03-06 08:26:43 -06:00
itm_syslog.h Remove whitespace and and carriage returns 2014-10-22 09:04:40 -06:00
itm.h Add ARMv7-M DWT and TPI register definitions 2014-10-21 16:46:26 -06:00
Kconfig ARMv7-M: Add toolchain option to select the IAR tools. Move ARMv7-M assembly language into a gnu/ subdirectory. Makefile selects iar/ or gnu/ directory based upon tool configuration 2016-04-02 07:53:52 -06:00
mpu.h Eliminate a warning due to a range check on an undefined pre-processar variable 2015-12-22 13:20:20 -06:00
nvic.h Break ARMv7E-M cache operations into separate files; Finish the unimplemented cache operations 2015-03-17 08:48:41 -06:00
psr.h Email address change in nuttx/ 2012-09-13 18:32:24 +00:00
ram_vectors.h Fixes a few more high priority, nested interrupt logic 2013-12-23 11:13:56 -06:00
svcall.h ARMv7-A/M: Cosmetic changes 2015-12-14 11:56:39 -06:00
Toolchain.defs ARMv7-M: Add toolchain option to select the IAR tools. Move ARMv7-M assembly language into a gnu/ subdirectory. Makefile selects iar/ or gnu/ directory based upon tool configuration 2016-04-02 07:53:52 -06:00
tpi.h Add ARMv7-M DWT and TPI register definitions 2014-10-21 16:46:26 -06:00
up_assert.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_blocktask.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_coherent_dcache.c Eliminate a warning 2015-12-12 11:37:25 -06:00
up_copyarmstate.c Add new common lazy FPU state saving option for ARMv7-M. Not yet verified 2015-03-06 08:26:43 -06:00
up_copyfullstate.c Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
up_doirq.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_elf.c All architectures need to build ELF support if either CONFIG_ELF or CONFIG_MODULE are selected. Cortex-M7 also must support module cache corherence 2015-12-12 09:35:05 -06:00
up_hardfault.c ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
up_initialstate.c Make some spacing comply better with coding standard 2015-10-06 16:23:32 -06:00
up_itm_syslog.c Correct some spacing issues 2015-10-07 11:39:06 -06:00
up_itm.c Standardize the width of all comment boxes in C files 2015-10-03 07:25:03 -06:00
up_memfault.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_mpu.c Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU 2015-12-14 13:56:21 -06:00
up_ramvec_attach.c Standard some naming if code sectino comments 2016-02-21 18:06:09 -06:00
up_ramvec_initialize.c Standard some naming if code sectino comments 2016-02-21 18:06:09 -06:00
up_releasepending.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_reprioritizertr.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_schedulesigaction.c ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
up_sigdeliver.c ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
up_signal_dispatch.c Move common/up_signal_dispatch.c to armv6-m, armv7-m, and armv7-a. The armv7-a version needs to be different to handle the case where we are dispatch kernel mode signals when running under a user mode group 2014-09-16 13:35:29 -06:00
up_stackcheck.c ARMv7-M: Cosmetic fixes to some file headers 2015-11-06 13:37:37 -06:00
up_svcall.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_systemreset.c Correct some spacing issues 2015-10-07 11:39:06 -06:00
up_unblocktask.c Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
up_vectors.c Costmetic fixes to C coding style 2015-10-05 17:13:53 -06:00