Tiago Medicci Serrano 6089f58f00 esp32s3/irq: Enhance IRQ subsystem ...

- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`

2023-08-14 16:29:21 -03:00

..

esp32

Fix nuttx coding style

2023-07-14 01:16:06 +08:00

esp32s2

arch/xtensa/esp32s2: Add support for RTC IRQs

2023-02-04 18:28:10 -03:00

esp32s3

esp32s3/irq: Enhance IRQ subsystem

2023-08-14 16:29:21 -03:00

lx6

arch: xtensa: Author Gregory Nutt: update licenses to Apache

2021-04-02 03:14:31 -05:00

lx7

xtensa: Add initial support for ESP32-S3

2022-01-27 13:46:50 -03:00

xtensa

Indent the define statement by two spaces

2023-05-21 09:52:08 -03:00

.gitignore

Remove exra whitespace from files (#189)

2020-01-31 09:24:49 -06:00

arch.h

mempool:Add mail_info support for multiple pools

2023-06-08 23:56:40 +08:00

elf.h

xtensa: Implement a few relocations

2020-03-16 07:54:49 -06:00

inttypes.h

arch: Omni Hoverboards: update licenses to Apache

2021-09-28 04:37:38 -07:00

irq.h

xtensa: Define COMMON_CTX_REGS for chips without FPU (e.g. ESP32-S2)

2022-10-27 23:28:47 +08:00

limits.h

arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h

2022-06-03 22:25:49 +03:00

loadstore.h

esp32: emulate byte access for module text

2020-03-16 07:54:49 -06:00

setjmp.h

xtensa: add setjmp.h include file

2021-11-17 02:23:45 -06:00

simcall.h

xtensa: Implement simcall

2020-03-12 09:03:31 -05:00

spinlock.h

arch&boards/xtensa: Fix some typos, references to STM/ARM code and

2020-08-27 05:48:55 -07:00

stdarg.h

arch:xtensa: add arch stdarg.h include file for xtensa

2021-08-09 17:58:25 -03:00

syscall.h

xtensa: Add missing input operand on sys_call6 inline ASM

2022-05-18 15:46:57 +02:00

types.h

arch: Add _wchar_t typedef like other basic types

2021-12-09 16:57:23 +09:00