Huang Qi 898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register ... If source register of sw instruction is x0, we must point it to a constant zero since in NuttX's context, value of index 0 is EPC. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2022-04-13 18:33:36 +08:00
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include	RISC-V: Combine 3 variables that depend on CPU amount into one	2022-04-12 01:59:35 +08:00
src	arch/risc-v/riscv_misaligned: Correct sw source register	2022-04-13 18:33:36 +08:00
Kconfig	arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa	2022-04-12 21:01:14 +03:00