nuttx

supervisor

RISC-V: Temporarily disable error about missing SBI

2022-05-02 16:13:15 +08:00

addrenv.h

RISC-V: Include support for kernel stack

2022-03-24 00:15:28 +08:00

crt0.c

arch: risc-v: Fix crt0.c if CONFIG_HAVE_CXX is not set

2022-05-23 21:19:01 +08:00

Make.defs

arch: Add up_nputs function to handle the non '\0' string correctly

2022-07-17 17:31:19 +03:00

pgalloc.h

RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe

2022-04-29 02:02:15 +08:00

riscv_addrenv_kstack.c

arch/risc-v: Remove FAR from chip and board folder

2022-04-19 00:22:45 +03:00

riscv_addrenv_perms.c

arch/addrenv: Change text write enable/disable to generic mprot

2022-05-12 22:28:31 +08:00

riscv_addrenv.c

Elf loader: give temporary write access to user .text memory

2022-05-03 21:25:25 +09:00

riscv_allocateheap.c

arch: Merge up_arch.h into up_internal.h

2022-03-14 09:32:17 +02:00

riscv_assert.c

arch: Remove the unnecessary #if/#endif in assert

2022-07-07 19:25:47 +03:00

riscv_backtrace.c

arch: Merge up_arch.h into up_internal.h

2022-03-14 09:32:17 +02:00

riscv_blocktask.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_checkstack.c

arch/risc-v: Remove the unnecessary inclusion of board header files

2022-04-07 11:25:12 +03:00

riscv_common_memorymap.h

risc-v: Move common memory map to its own file from riscv_internal

2022-06-28 14:41:56 +03:00

riscv_copystate.c

arch/risc-v: Store/Restore FPU register in exception_common

2022-03-31 11:49:36 +08:00

riscv_cpuidlestack.c

risc-v: Let g_cpu_basestack determined at compile time

2022-02-15 11:40:34 +09:00

riscv_cpuindex.c

RISC-V: Move mhartid to own assembly macro+function

2022-04-13 12:00:40 +02:00

riscv_cpupause.c

arch: Merge up_arch.h into up_internal.h

2022-03-14 09:32:17 +02:00

riscv_cpustart.c

arch/risc-v: Correct stack coloration in riscv_cpu_boot

2022-03-16 14:12:45 +02:00

riscv_createstack.c

arch/stack_color: correct the stack top of running task

2022-04-14 16:48:19 +08:00

riscv_doirq.c

arch/risc-v: Move epc adjustment to riscv_doirq

2022-04-10 00:52:04 +08:00

riscv_exception_common.S

arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place

2022-07-04 13:25:56 +03:00

riscv_exception.c

arch/risc-v: Apply misaligned access handler for k210/bl602

2022-04-13 01:10:49 +08:00

riscv_exit.c

arch: Move the DUMP_ON_EXIT logic after nxtask_exit.

2022-04-13 21:59:23 +08:00

riscv_fpu.S

arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig

2022-04-21 15:26:05 +08:00

riscv_fpucmp.c

board/arch_fpu*: move arch_[get|cmp]fpu to common arch

2022-04-18 22:22:16 +08:00

riscv_getnewintctx.c

RISC-V: Implement option to run NuttX in supervisor mode (S-mode)

2022-04-01 16:19:42 -03:00

riscv_hostfs.c

fs: Make the binary(no process) mode as the default

2022-06-07 20:22:26 +03:00

riscv_idle.c

risc-v: Support cpu activity led in up_idle

2022-02-10 13:09:32 +08:00

riscv_initialize.c

netinitialize: call xxx_netinitialize unconditionally

2022-03-19 17:41:33 +08:00

riscv_initialstate.c

arch/risc-v: Improve performance of context switch

2022-03-26 07:19:09 +09:00

riscv_internal.h

arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place

2022-07-04 13:25:56 +03:00

riscv_macros.S

arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro

2022-04-20 16:08:17 +03:00

riscv_mdelay.c

arch: risc-V: Author Gregory Nutt: update licenses to Apache

2021-03-31 08:48:51 -07:00

riscv_mhartid.S

RISC-V: Move mhartid to own assembly macro+function

2022-04-13 12:00:40 +02:00

riscv_misaligned.c

arch/risc-v/riscv_misaligned: Implement float load/store support

2022-04-22 12:23:10 +08:00

riscv_mmu.c

Elf loader: give temporary write access to user .text memory

2022-05-03 21:25:25 +09:00

riscv_mmu.h

Elf loader: give temporary write access to user .text memory

2022-05-03 21:25:25 +09:00

riscv_modifyreg32.c

arch: Merge up_arch.h into up_internal.h

2022-03-14 09:32:17 +02:00

riscv_mtimer.c

RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs.

2022-04-27 22:48:54 +08:00

riscv_mtimer.h

arch/riscv: Add mtimer driver

2022-04-11 10:59:18 +03:00

riscv_nputs.c

arch: Add up_nputs function to handle the non '\0' string correctly

2022-07-17 17:31:19 +03:00

riscv_percpu.c

RISC-V: Combine 3 variables that depend on CPU amount into one

2022-04-12 01:59:35 +08:00

riscv_percpu.h

RISC-V: Combine 3 variables that depend on CPU amount into one

2022-04-12 01:59:35 +08:00

riscv_pgalloc.c

RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe

2022-04-29 02:02:15 +08:00

riscv_pmp.c

riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.

2022-05-08 00:26:24 +03:00

riscv_pthread_start.c

arch: Move the content from svcall.h to syscall.h

2022-02-27 22:54:13 +08:00

riscv_releasepending.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_releasestack.c

arch/risc-v: Remove FAR qualifier for RISC-V-specific files

2021-09-22 08:16:01 -03:00

riscv_reprioritizertr.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_saveusercontext.c

arch/risc-v: Remove FAR from chip and board folder

2022-04-19 00:22:45 +03:00

riscv_schedulesigaction.c

arch: Remove "0x" prefix preceding "%p" specifier on format string

2022-06-30 22:08:58 +03:00

riscv_semihost.S

arch: risc-v: Add support for semihosting and hostfs

2022-05-02 19:46:58 +08:00

riscv_sigdeliver.c

Remove the unneeded void cast

2022-04-17 23:32:05 +03:00

riscv_signal_dispatch.c

arch: Move the content from svcall.h to syscall.h

2022-02-27 22:54:13 +08:00

riscv_signal_handler.S

arch/risc-v: get wider visibility for arch instruction macros

2022-04-01 10:31:24 +08:00

riscv_stackframe.c

arch: Move STACK_ALIGNMENT definition to up_internal.h

2022-02-28 15:05:41 +08:00

riscv_swint.c

arch/riscv: Remove & ~1 before assign signal_handler to REG_EPC

2022-05-12 23:31:50 +03:00

riscv_task_start.c

arch: Move the content from svcall.h to syscall.h

2022-02-27 22:54:13 +08:00

riscv_tcbinfo.c

arch:tcbinfo: update tcbinfo as xcpcontext update

2022-04-05 13:33:00 +02:00

riscv_testset.S

arch/risc-v: Refine riscv_testset.S

2021-12-29 06:06:01 -06:00

riscv_tls.c

assert: unify stack and register dump across platforms

2021-12-20 00:02:12 -03:00

riscv_udelay.c

arch: risc-V: Author Gregory Nutt: update licenses to Apache

2021-03-31 08:48:51 -07:00

riscv_unblocktask.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_usestack.c

arch: Move STACK_ALIGNMENT definition to up_internal.h

2022-02-28 15:05:41 +08:00

riscv_vectors.S

RISC-V: Implement option to run NuttX in supervisor mode (S-mode)

2022-04-01 16:19:42 -03:00

riscv_vfork.c

risc-v/vfork: Save FPU registers

2022-05-19 09:05:00 -03:00

riscv_vfork.h

risc-v/vfork: FPU was not saved correctly

2022-05-20 15:59:24 +08:00

Toolchain.defs

this flag is meaningless for the linker

2022-06-27 20:03:03 -03:00

vfork.S

risc-v/vfork: FPU was not saved correctly

2022-05-20 15:59:24 +08:00