zhuyanlin f5d180bbdf xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO ... For up_irq_disable, use XCHAL_EXCM_LEVEL For up_irq_save, use XCHAL_IRQ_LEVEL. Then we can use svcall in enter_crritical_section. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>		2022-02-25 20:43:03 +08:00
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core_macros.h	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
core.h	xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO	2022-02-25 20:43:03 +08:00
xtensa_abi.h	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
xtensa_coproc.h	xtensa: fix lack of float register save & resotre	2022-01-11 12:17:09 +01:00
xtensa_corebits.h	arch: xtensa: fix nxstyle errors	2021-04-07 21:21:51 -05:00
xtensa_specregs.h	Appease many of nxstyle errors for esp32 related files	2020-03-12 07:45:44 -06:00