sergiotarxz/nuttx
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nuttx/arch/xtensa/include
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zhuyanlin fbc1da98b7 xtensa: use swint to swith context 
Reason for use sw-interrupt as syscall interrupt:
The xtensa `syscall` instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter `enter_critical_section` and gerenate
interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-25 20:43:03 +08:00
..
esp32
xtensa:esp32: setup software interrupt. (bit 29)
2022-02-24 00:06:43 +01:00
esp32s2
xtensa:esp32s2: setup software interrupt as swi interrupt
2022-02-24 00:06:43 +01:00
esp32s3
xtensa:esp32s3: setup software interrupt as swi interrupt.
2022-02-24 00:06:43 +01:00
lx6
arch: xtensa: Author Gregory Nutt: update licenses to Apache
2021-04-02 03:14:31 -05:00
lx7
xtensa: Add initial support for ESP32-S3
2022-01-27 13:46:50 -03:00
xtensa
xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO
2022-02-25 20:43:03 +08:00
.gitignore
Remove exra whitespace from files (#189)
2020-01-31 09:24:49 -06:00
arch.h
arch/xtensa: Remove FAR qualifier for Xtensa-specific files
2021-09-22 08:16:01 -03:00
elf.h
xtensa: Implement a few relocations
2020-03-16 07:54:49 -06:00
inttypes.h
arch: Omni Hoverboards: update licenses to Apache
2021-09-28 04:37:38 -07:00
irq.h
xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO
2022-02-25 20:43:03 +08:00
limits.h
arch: xtensa: Author Gregory Nutt: update licenses to Apache
2021-04-02 03:14:31 -05:00
loadstore.h
esp32: emulate byte access for module text
2020-03-16 07:54:49 -06:00
setjmp.h
xtensa: add setjmp.h include file
2021-11-17 02:23:45 -06:00
simcall.h
xtensa: Implement simcall
2020-03-12 09:03:31 -05:00
spinlock.h
arch&boards/xtensa: Fix some typos, references to STM/ARM code and
2020-08-27 05:48:55 -07:00
stdarg.h
arch:xtensa: add arch stdarg.h include file for xtensa
2021-08-09 17:58:25 -03:00
syscall.h
xtensa: use swint to swith context
2022-02-25 20:43:03 +08:00
types.h
arch: Add _wchar_t typedef like other basic types
2021-12-09 16:57:23 +09:00