2016-10-12 21:11:05 +02:00
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_XTENSA
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choice
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prompt "XTENSA architecture selection"
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2016-10-13 22:37:28 +02:00
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default ARCH_CHIP_ESP32
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2016-10-12 21:11:05 +02:00
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2016-10-13 22:37:28 +02:00
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config ARCH_CHIP_ESP32
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bool "Expressif ESP32"
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select ARCH_FAMILY_LX6
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2016-10-15 18:11:35 +02:00
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select XTENSA_HAVE_INTERRUPTS
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2016-10-12 21:11:05 +02:00
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---help---
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2016-10-13 22:37:28 +02:00
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The ESP32 is a dual-core system from Expressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory
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and peripherals are located on the data bus and/or the instruction
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bus of these CPUs. With some minor exceptions, the address mapping
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of two CPUs is symmetric, meaning they use the same addresses to
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access the same memory.
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2016-10-12 21:11:05 +02:00
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endchoice # XTENSA chip selection
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2016-10-13 22:37:28 +02:00
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config ARCH_FAMILY_LX6
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2016-10-12 21:11:05 +02:00
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bool
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default n
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2016-10-13 22:37:28 +02:00
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---help---
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Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
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The LX6 is a configurable and extensible processor core.
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2016-10-12 21:11:05 +02:00
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2016-10-14 21:17:48 +02:00
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config XTENSA_HAVE_LOOPS
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bool "Zero overhead loops"
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default n
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2016-10-15 18:11:35 +02:00
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config XTENSA_HAVE_INTERRUPTS
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bool
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default n
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2016-10-14 21:17:48 +02:00
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config XTENSA_USE_SWPRI
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bool "Use SWPRI"
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default n
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config XTENSA_CALL0_ABI
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bool "CALL0 ABI"
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default y
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config XTENSA_USE_OVLY
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bool "Use overlay"
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default n
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2016-10-12 21:11:05 +02:00
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config ARCH_CHIP
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string
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2016-10-13 22:37:28 +02:00
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default "esp32" if ARCH_CHIP_ESP32
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2016-10-12 21:11:05 +02:00
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source arch/xtensa/src/lx6/Kconfig
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endif # ARCH_XTENSA
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