2022-06-09 22:34:30 +02:00
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/****************************************************************************
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2022-12-05 02:22:43 +01:00
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* boards/xtensa/esp32s3/common/scripts/legacy_sections.ld
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2023-01-18 17:59:48 +01:00
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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2022-06-09 22:34:30 +02:00
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****************************************************************************/
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2023-02-08 13:43:29 +01:00
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#include <nuttx/config.h>
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2022-06-09 22:34:30 +02:00
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/* Default entry point: */
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ENTRY(__start);
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_diram_i_start = 0x40378000;
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SECTIONS
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{
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/* Send .iram0 code to iram */
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.iram0.vectors :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to IRAM. */
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_init_start = ABSOLUTE(.);
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/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
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. = 0x0;
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KEEP (*(.window_vectors.text));
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. = 0x180;
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KEEP (*(.xtensa_level2_vector.text));
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. = 0x1c0;
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KEEP (*(.xtensa_level3_vector.text));
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. = 0x200;
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KEEP (*(.xtensa_level4_vector.text));
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. = 0x240;
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KEEP (*(.xtensa_level5_vector.text));
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. = 0x280;
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KEEP (*(.debug_exception_vector.text));
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. = 0x2c0;
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KEEP (*(.nmi_vector.text));
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. = 0x300;
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KEEP (*(.kernel_exception_vector.text));
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. = 0x340;
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KEEP (*(.user_exception_vector.text));
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. = 0x3c0;
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KEEP (*(.double_exception_vector.text));
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. = 0x400;
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*(.*_vector.literal)
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. = ALIGN(16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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2022-10-31 22:43:58 +01:00
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} >iram0_0_seg
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2022-06-09 22:34:30 +02:00
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.iram0.text :
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{
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/* Code marked as running out of IRAM */
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*(.iram1 .iram1.*)
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2023-09-13 14:10:06 +02:00
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*libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
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*libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
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2023-09-20 20:33:28 +02:00
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*libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
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2023-05-19 21:37:52 +02:00
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*libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
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2023-09-13 14:10:06 +02:00
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*libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
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2023-05-19 21:37:52 +02:00
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*libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
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2023-09-13 14:10:06 +02:00
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*libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
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2023-05-19 21:37:52 +02:00
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*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
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2023-09-20 20:33:28 +02:00
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#ifdef CONFIG_ESP32S3_BLE
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2023-11-06 12:03:28 +01:00
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*libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
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2023-09-20 20:33:28 +02:00
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#endif
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2023-09-13 14:10:06 +02:00
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*libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
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*libsched.a:assert.*(.literal .text .literal.* .text.*)
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2023-05-19 21:37:52 +02:00
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*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
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*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
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2023-09-13 14:10:06 +02:00
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*libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
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2023-05-19 21:37:52 +02:00
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*libsched.a:sched_note.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
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*libsched.a:spinlock.*(.literal .text .literal.* .text.*)
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2023-08-25 13:32:02 +02:00
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#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
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*libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context)
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*libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr)
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*libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle)
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*libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \
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.literal.esp32s3_dma_enable .text.esp32s3_dma_enable)
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*libsched.a:sched_processtimer.*(.literal.nxsched_process_timer .text.nxsched_process_timer)
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*libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer)
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*libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer)
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*libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin .text.nxsched_process_roundrobin)
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*libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr .text.nxsched_reprioritize_rtr)
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*libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun .text.nxsched_remove_readytorun)
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*libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun .text.nxsched_add_readytorun)
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*libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized .text.nxsched_add_prioritized)
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*libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending .text.nxsched_merge_pending)
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*libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler .text.nxsched_resume_scheduler)
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2023-11-06 12:03:28 +01:00
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*libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst)
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2023-08-25 13:32:02 +02:00
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#endif
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2023-10-23 11:32:21 +02:00
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*libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*)
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#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
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*libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*)
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#endif
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#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
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*libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*)
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#endif
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2023-10-17 04:11:12 +02:00
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#if defined(CONFIG_STACK_CANARIES) && \
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(defined(CONFIG_ESP32S3_SPIFLASH) || \
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defined(CONFIG_ESP32S3_SPIRAM))
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*libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
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#endif
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2023-02-08 13:43:29 +01:00
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*(.wifirxiram .wifirxiram.*)
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*(.wifi0iram .wifi0iram.*)
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*(.wifiorslpiram .wifiorslpiram.*)
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*(.wifislpiram .wifislpiram.*)
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*(.wifislprxiram .wifislprxiram.*)
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*(.phyiram .phyiram.*)
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2022-06-09 22:34:30 +02:00
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/* align + add 16B for CPU dummy speculative instr. fetch */
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. = ALIGN(4) + 16;
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_iram_text = ABSOLUTE(.);
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2022-10-31 22:43:58 +01:00
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} >iram0_0_seg
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2022-06-09 22:34:30 +02:00
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.dram0.dummy (NOLOAD) :
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{
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/* This section is required to skip .iram0.text area because iram0_0_seg
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* and dram0_0_seg reflect the same address space on different buses.
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*/
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2022-08-24 21:11:34 +02:00
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. = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
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2022-10-31 22:43:58 +01:00
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} >dram0_0_seg
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2022-06-09 22:34:30 +02:00
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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/* .bss initialized on power-up */
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. = ALIGN(8);
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(COMMON)
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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. = ALIGN(8);
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_ebss = ABSOLUTE(.);
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2022-10-31 22:43:58 +01:00
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} >dram0_0_seg
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2022-06-09 22:34:30 +02:00
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.noinit (NOLOAD) :
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{
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/* This section contains data that is not initialized during load,
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* or during the application's initialization sequence.
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*/
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. = ALIGN(4);
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*(.noinit .noinit.*)
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. = ALIGN(4);
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2022-10-31 22:43:58 +01:00
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} >dram0_0_seg
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2022-06-09 22:34:30 +02:00
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.dram0.data :
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{
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/* .data initialized on power-up in ROMed configurations. */
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_sdata = ABSOLUTE(.);
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KEEP (*(.data))
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KEEP (*(.data.*))
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KEEP (*(.gnu.linkonce.d.*))
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KEEP (*(.data1))
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KEEP (*(.sdata))
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KEEP (*(.sdata.*))
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KEEP (*(.gnu.linkonce.s.*))
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KEEP (*(.sdata2))
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KEEP (*(.sdata2.*))
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KEEP (*(.gnu.linkonce.s2.*))
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KEEP (*(.jcr))
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*(.dram1 .dram1.*)
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2023-02-08 13:43:29 +01:00
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*libphy.a:(.rodata .rodata.*)
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2023-09-13 14:10:06 +02:00
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*libarch.a:xtensa_context.*(.rodata .rodata.*)
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2023-10-17 04:11:12 +02:00
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#if defined(CONFIG_STACK_CANARIES) && \
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(defined(CONFIG_ESP32S3_SPIFLASH) || \
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defined(CONFIG_ESP32S3_SPIRAM))
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*libc.a:lib_stackchk.*(.rodata .rodata.*)
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#endif
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2023-02-08 13:43:29 +01:00
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2022-06-09 22:34:30 +02:00
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_edata = ABSOLUTE(.);
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. = ALIGN(4);
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/* Heap starts at the end of .data */
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_sheap = ABSOLUTE(.);
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2022-10-31 22:43:58 +01:00
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} >dram0_0_seg
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2022-06-09 22:34:30 +02:00
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.flash.text :
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{
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_stext = .;
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/* CPU will try to prefetch up to 16 bytes of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_etext = .;
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2022-10-31 22:43:58 +01:00
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} >default_code_seg
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2022-06-09 22:34:30 +02:00
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.flash_rodata_dummy (NOLOAD) :
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{
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/* This dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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/* Start at the same alignment constraint than .flash.text */
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. = ALIGN(ALIGNOF(.flash.text));
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/* Create an empty gap as big as .flash.text section */
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. = SIZEOF(.flash.text);
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/* Prepare the alignment of the section above. Few bytes (0x20) must be
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* added for the mapping header.
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*/
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. = ALIGN(0x10000) + 0x20;
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_rodata_reserved_start = .;
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2022-10-31 22:43:58 +01:00
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} >default_rodata_seg
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2022-06-09 22:34:30 +02:00
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.flash.rodata : ALIGN(0x10)
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{
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_srodata = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
|
2023-02-08 13:43:29 +01:00
|
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#ifdef CONFIG_ESP32S3_WIRELESS
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|
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*(.rodata_wlog_verbose.*)
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*(.rodata_wlog_debug.*)
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*(.rodata_wlog_info.*)
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*(.rodata_wlog_warning.*)
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*(.rodata_wlog_error.*)
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#endif
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2022-06-09 22:34:30 +02:00
|
|
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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. = ALIGN(4);
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/* C++ constructor and destructor tables, properly ordered: */
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_sinit = ABSOLUTE(.);
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KEEP (*crtbegin.o(.ctors))
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|
|
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
|
|
|
KEEP (*(SORT(.ctors.*)))
|
|
|
|
KEEP (*(.ctors))
|
|
|
|
_einit = ABSOLUTE(.);
|
|
|
|
KEEP (*crtbegin.o(.dtors))
|
|
|
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
|
|
|
KEEP (*(SORT(.dtors.*)))
|
|
|
|
KEEP (*(.dtors))
|
|
|
|
|
|
|
|
/* C++ exception handlers table: */
|
|
|
|
|
|
|
|
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
|
|
|
*(.xt_except_desc)
|
|
|
|
*(.gnu.linkonce.h.*)
|
|
|
|
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
|
|
|
*(.xt_except_desc_end)
|
|
|
|
*(.dynamic)
|
|
|
|
*(.gnu.version_d)
|
|
|
|
_erodata = ABSOLUTE(.);
|
|
|
|
|
|
|
|
/* Literals are also RO data. */
|
|
|
|
|
|
|
|
_lit4_start = ABSOLUTE(.);
|
|
|
|
*(*.lit4)
|
|
|
|
*(.lit4.*)
|
|
|
|
*(.gnu.linkonce.lit4.*)
|
|
|
|
_lit4_end = ABSOLUTE(.);
|
|
|
|
_rodata_reserved_end = ABSOLUTE(.);
|
|
|
|
. = ALIGN(4);
|
2022-10-31 22:43:58 +01:00
|
|
|
} >default_rodata_seg
|
2022-06-09 22:34:30 +02:00
|
|
|
|
|
|
|
/* Marks the end of IRAM code segment */
|
|
|
|
|
|
|
|
.iram0.text_end (NOLOAD) :
|
|
|
|
{
|
|
|
|
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
|
|
|
|
* 256B alignment for PMS split lines.
|
|
|
|
*/
|
|
|
|
|
|
|
|
. += 16;
|
|
|
|
. = ALIGN(256);
|
2022-10-31 22:43:58 +01:00
|
|
|
} >iram0_0_seg
|
2022-06-09 22:34:30 +02:00
|
|
|
|
|
|
|
.iram0.data :
|
|
|
|
{
|
|
|
|
. = ALIGN(4);
|
|
|
|
|
|
|
|
*(.iram.data)
|
|
|
|
*(.iram.data.*)
|
2022-10-31 22:43:58 +01:00
|
|
|
} >iram0_0_seg
|
2022-06-09 22:34:30 +02:00
|
|
|
|
|
|
|
.iram0.bss (NOLOAD) :
|
|
|
|
{
|
|
|
|
. = ALIGN(4);
|
|
|
|
|
|
|
|
*(.iram.bss)
|
|
|
|
*(.iram.bss.*)
|
|
|
|
|
|
|
|
. = ALIGN(4);
|
|
|
|
_iram_end = ABSOLUTE(.);
|
2022-10-31 22:43:58 +01:00
|
|
|
} >iram0_0_seg
|
2023-11-10 17:41:07 +01:00
|
|
|
|
|
|
|
.rtc.data :
|
|
|
|
{
|
|
|
|
*(.rtc.data)
|
|
|
|
*(.rtc.rodata)
|
|
|
|
|
|
|
|
/* Whatever is left from the RTC memory is used as a special heap. */
|
|
|
|
|
|
|
|
. = ALIGN (4);
|
|
|
|
_srtcheap = ABSOLUTE(.);
|
|
|
|
} > rtc_slow_seg
|
2022-06-09 22:34:30 +02:00
|
|
|
}
|