2011-03-26 02:04:10 +01:00
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/************************************************************************************
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2017-02-26 16:15:57 +01:00
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* arch/arm/src/stm32/stm32_tim.c
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2011-03-26 02:04:10 +01:00
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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2011-12-16 20:29:41 +01:00
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* With modifications and updates by:
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*
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2012-01-13 03:49:10 +01:00
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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2011-12-16 20:29:41 +01:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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2011-03-26 02:04:10 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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2011-12-16 20:29:41 +01:00
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/************************************************************************************
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* Included Files
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************************************************************************************/
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2011-03-26 02:04:10 +01:00
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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2013-02-09 16:03:49 +01:00
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#include "stm32.h"
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2011-03-26 02:04:10 +01:00
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#include "stm32_gpio.h"
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#include "stm32_tim.h"
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2011-12-16 20:29:41 +01:00
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/************************************************************************************
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2016-07-06 21:36:17 +02:00
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* Pre-processor Definitions
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2011-12-16 20:29:41 +01:00
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************************************************************************************/
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2016-07-06 21:36:17 +02:00
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2011-12-16 20:29:41 +01:00
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. Such special purposes include:
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*
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* - To generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
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* is defined then the CONFIG_STM32_TIMn_PWM may also be defined to indicate that
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* the timer is intended to be used for pulsed output modulation.
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*
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2012-01-13 03:49:10 +01:00
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* - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is defined then
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2011-12-16 20:29:41 +01:00
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* CONFIG_STM32_TIMn_ADC may also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*
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2012-01-13 03:49:10 +01:00
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* - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then
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2011-12-16 20:29:41 +01:00
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* CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*
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2012-02-14 18:48:25 +01:00
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* - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*
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2011-12-16 20:29:41 +01:00
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* In any of these cases, the timer will not be used by this timer module.
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*/
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \
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defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM1
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \
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defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM2
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \
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defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM3
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \
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defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM4
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \
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defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM5
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
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defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM6
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \
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defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM7
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \
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defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM8
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \
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defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM9
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \
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defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM10
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \
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defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM11
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \
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defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM12
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \
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defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM13
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#endif
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2012-02-14 18:48:25 +01:00
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#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \
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defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE)
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2011-12-16 20:29:41 +01:00
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# undef CONFIG_STM32_TIM14
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#endif
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2016-06-03 21:51:43 +02:00
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#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
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defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE)
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# undef CONFIG_STM32_TIM15
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#endif
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#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \
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defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
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# undef CONFIG_STM32_TIM16
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \
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defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE)
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# undef CONFIG_STM32_TIM17
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#endif
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2011-12-16 20:29:41 +01:00
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2016-07-11 21:13:17 +02:00
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#undef HAVE_TIM_GPIOCONFIG
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM1)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
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defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM1_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM2)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
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defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM2_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM3)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
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defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM3_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM4)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
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defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM4_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM5)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
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defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM5_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM8)
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2015-10-31 15:33:32 +01:00
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# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
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defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
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2016-07-11 21:13:17 +02:00
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# undef HAVE_TIM_GPIOCONFIG
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# define HAVE_TIM_GPIOCONFIG 1
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2015-10-31 15:59:20 +01:00
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# define HAVE_TIM8_GPIOCONFIG 1
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2015-10-31 15:33:32 +01:00
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM9)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\
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defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT)
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# define HAVE_TIM9_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM10)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\
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defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT)
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# define HAVE_TIM10_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM11)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\
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defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT)
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# define HAVE_TIM11_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM12)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\
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defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT)
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# define HAVE_TIM12_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM13)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\
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defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT)
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# define HAVE_TIM13_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM14)
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2016-06-03 21:51:43 +02:00
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# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\
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defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT)
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# define HAVE_TIM14_GPIOCONFIG 1
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#endif
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#endif
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2016-06-03 22:08:28 +02:00
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#if defined(CONFIG_STM32_TIM15)
|
2016-06-03 21:51:43 +02:00
|
|
|
# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
|
|
|
|
defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
|
|
|
|
# define HAVE_TIM15_GPIOCONFIG 1
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-06-03 22:08:28 +02:00
|
|
|
#if defined(CONFIG_STM32_TIM16)
|
2016-06-03 21:51:43 +02:00
|
|
|
# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
|
|
|
|
defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
|
|
|
|
# define HAVE_TIM16_GPIOCONFIG 1
|
|
|
|
#endif
|
|
|
|
#endif
|
2015-10-31 15:33:32 +01:00
|
|
|
|
2016-06-03 22:08:28 +02:00
|
|
|
#if defined(CONFIG_STM32_TIM17)
|
|
|
|
# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\
|
|
|
|
defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT)
|
|
|
|
# define HAVE_TIM17_GPIOCONFIG 1
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2011-12-16 20:29:41 +01:00
|
|
|
/* This module then only compiles if there are enabled timers that are not intended for
|
|
|
|
* some other purpose.
|
|
|
|
*/
|
|
|
|
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
|
|
|
|
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
|
|
|
|
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
|
|
|
|
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
|
|
|
|
defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \
|
|
|
|
defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \
|
|
|
|
defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \
|
2016-06-03 22:08:28 +02:00
|
|
|
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
|
|
|
|
defined(CONFIG_STM32_TIM17)
|
2011-03-26 02:04:10 +01:00
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Private Types
|
|
|
|
************************************************************************************/
|
|
|
|
|
2012-01-13 03:49:10 +01:00
|
|
|
/* TIM Device Structure */
|
|
|
|
|
|
|
|
struct stm32_tim_priv_s
|
|
|
|
{
|
2016-07-06 21:36:17 +02:00
|
|
|
const struct stm32_tim_ops_s *ops;
|
|
|
|
stm32_tim_mode_t mode;
|
|
|
|
uint32_t base; /* TIMn base address */
|
2011-03-26 02:04:10 +01:00
|
|
|
};
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Private Function prototypes
|
|
|
|
************************************************************************************/
|
|
|
|
|
2016-07-06 22:24:59 +02:00
|
|
|
/* Register helpers */
|
|
|
|
|
|
|
|
static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset);
|
|
|
|
static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
|
|
|
|
uint16_t value);
|
|
|
|
static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset, uint16_t clearbits,
|
|
|
|
uint16_t setbits);
|
|
|
|
static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset);
|
|
|
|
static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
|
|
|
|
uint32_t value);
|
|
|
|
|
|
|
|
/* Timer helpers */
|
|
|
|
|
|
|
|
static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev);
|
|
|
|
static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev);
|
|
|
|
static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev);
|
|
|
|
static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev);
|
2016-07-11 21:13:17 +02:00
|
|
|
|
|
|
|
#ifdef HAVE_TIM_GPIOCONFIG
|
2016-07-06 22:24:59 +02:00
|
|
|
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode);
|
2016-07-11 21:13:17 +02:00
|
|
|
#endif
|
2016-07-06 22:24:59 +02:00
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/* Timer methods */
|
|
|
|
|
2017-05-08 20:33:15 +02:00
|
|
|
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
|
|
|
|
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
|
2016-07-06 21:36:17 +02:00
|
|
|
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint32_t period);
|
|
|
|
static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev);
|
2017-05-08 20:33:15 +02:00
|
|
|
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev);
|
|
|
|
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
|
|
|
|
stm32_tim_channel_t mode);
|
|
|
|
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
|
|
|
|
uint32_t compare);
|
|
|
|
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
|
|
|
|
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
|
|
|
|
void *arg, int source);
|
2016-07-06 21:36:17 +02:00
|
|
|
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source);
|
|
|
|
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source);
|
|
|
|
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source);
|
2017-05-08 20:33:15 +02:00
|
|
|
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source);
|
2016-07-06 21:36:17 +02:00
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Private Data
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static const struct stm32_tim_ops_s stm32_tim_ops =
|
|
|
|
{
|
|
|
|
.setmode = stm32_tim_setmode,
|
|
|
|
.setclock = stm32_tim_setclock,
|
|
|
|
.setperiod = stm32_tim_setperiod,
|
|
|
|
.getcounter = stm32_tim_getcounter,
|
2017-05-08 20:33:15 +02:00
|
|
|
.getwidth = stm32_tim_getwidth,
|
2016-07-06 21:36:17 +02:00
|
|
|
.setchannel = stm32_tim_setchannel,
|
|
|
|
.setcompare = stm32_tim_setcompare,
|
|
|
|
.getcapture = stm32_tim_getcapture,
|
|
|
|
.setisr = stm32_tim_setisr,
|
|
|
|
.enableint = stm32_tim_enableint,
|
|
|
|
.disableint = stm32_tim_disableint,
|
|
|
|
.ackint = stm32_tim_ackint,
|
|
|
|
.checkint = stm32_tim_checkint,
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM1
|
|
|
|
struct stm32_tim_priv_s stm32_tim1_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM1_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM2
|
|
|
|
struct stm32_tim_priv_s stm32_tim2_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM2_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM3
|
|
|
|
struct stm32_tim_priv_s stm32_tim3_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM3_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM4
|
|
|
|
struct stm32_tim_priv_s stm32_tim4_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM4_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM5
|
|
|
|
struct stm32_tim_priv_s stm32_tim5_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM5_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM6
|
|
|
|
struct stm32_tim_priv_s stm32_tim6_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM6_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM7
|
|
|
|
struct stm32_tim_priv_s stm32_tim7_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM7_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM8
|
|
|
|
struct stm32_tim_priv_s stm32_tim8_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM8_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM9
|
|
|
|
struct stm32_tim_priv_s stm32_tim9_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM9_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM10
|
|
|
|
struct stm32_tim_priv_s stm32_tim10_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM10_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM11
|
|
|
|
struct stm32_tim_priv_s stm32_tim11_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM11_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM12
|
|
|
|
struct stm32_tim_priv_s stm32_tim12_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM12_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM13
|
|
|
|
struct stm32_tim_priv_s stm32_tim13_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM13_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM14
|
|
|
|
struct stm32_tim_priv_s stm32_tim14_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM14_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM15
|
|
|
|
struct stm32_tim_priv_s stm32_tim15_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM15_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM16
|
|
|
|
struct stm32_tim_priv_s stm32_tim16_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM16_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_TIM17
|
|
|
|
struct stm32_tim_priv_s stm32_tim17_priv =
|
|
|
|
{
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM17_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
/************************************************************************************
|
|
|
|
* Private Functions
|
|
|
|
************************************************************************************/
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_getreg16
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Get a 16-bit register value by offset
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset)
|
2012-01-13 03:49:10 +01:00
|
|
|
{
|
|
|
|
return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset);
|
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_putreg16
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Put a 16-bit register value by offset
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
|
|
|
|
uint16_t value)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_modifyreg16
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Modify a 16-bit register value by offset
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset, uint16_t clearbits,
|
|
|
|
uint16_t setbits)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_getreg32
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Get a 32-bit register value by offset. This applies only for the STM32 F4
|
|
|
|
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint8_t offset)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset);
|
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_putreg32
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Put a 32-bit register value by offset. This applies only for the STM32 F4
|
|
|
|
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
|
|
|
|
uint32_t value)
|
2012-01-13 03:49:10 +01:00
|
|
|
{
|
|
|
|
putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_reload_counter
|
|
|
|
************************************************************************************/
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET);
|
|
|
|
val |= ATIM_EGR_UG;
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_enable
|
|
|
|
************************************************************************************/
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
|
|
|
|
val |= ATIM_CR1_CEN;
|
|
|
|
stm32_tim_reload_counter(dev);
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_disable
|
|
|
|
************************************************************************************/
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
|
|
|
|
val &= ~ATIM_CR1_CEN;
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_reset
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Reset timer into system default state, but do not affect output/input pins
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2013-12-22 20:23:57 +01:00
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
|
|
|
|
stm32_tim_disable(dev);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_gpioconfig
|
|
|
|
************************************************************************************/
|
|
|
|
|
2016-07-11 21:13:17 +02:00
|
|
|
#ifdef HAVE_TIM_GPIOCONFIG
|
2011-03-27 17:03:49 +02:00
|
|
|
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
|
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
/* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
|
2011-03-27 17:03:49 +02:00
|
|
|
|
2012-01-13 03:49:10 +01:00
|
|
|
if (mode & STM32_TIM_CH_MODE_MASK)
|
|
|
|
{
|
|
|
|
stm32_configgpio(cfg);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
stm32_unconfiggpio(cfg);
|
2011-03-27 17:03:49 +02:00
|
|
|
}
|
|
|
|
}
|
2015-10-31 15:33:32 +01:00
|
|
|
#endif
|
2011-03-27 17:03:49 +02:00
|
|
|
|
2016-07-06 22:24:59 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_setmode
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode)
|
|
|
|
{
|
|
|
|
uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
|
|
|
|
/* This function is not supported on basic timers. To enable or
|
|
|
|
* disable it, simply set its clock to valid frequency or zero.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Decode operational modes */
|
|
|
|
|
|
|
|
switch (mode & STM32_TIM_MODE_MASK)
|
|
|
|
{
|
|
|
|
case STM32_TIM_MODE_DISABLED:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_DOWN:
|
|
|
|
val |= ATIM_CR1_DIR;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_UP:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_UPDOWN:
|
|
|
|
val |= ATIM_CR1_CENTER1;
|
|
|
|
// Our default: Interrupts are generated on compare, when counting down
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_PULSE:
|
|
|
|
val |= ATIM_CR1_OPM;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
stm32_tim_reload_counter(dev);
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
|
|
|
|
|
|
|
|
#if STM32_NATIM > 0
|
|
|
|
/* Advanced registers require Main Output Enable */
|
|
|
|
|
|
|
|
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
|
|
|
|
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
|
|
|
|
{
|
|
|
|
stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
/************************************************************************************
|
2016-07-06 21:36:17 +02:00
|
|
|
* Name: stm32_tim_setclock
|
2011-03-26 02:04:10 +01:00
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
|
|
|
|
{
|
2016-06-03 19:38:59 +02:00
|
|
|
uint32_t freqin;
|
2012-01-13 03:49:10 +01:00
|
|
|
int prescaler;
|
|
|
|
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Disable Timer? */
|
|
|
|
|
|
|
|
if (freq == 0)
|
|
|
|
{
|
|
|
|
stm32_tim_disable(dev);
|
|
|
|
return 0;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2016-06-03 19:38:59 +02:00
|
|
|
/* Get the input clock frequency for this timer. These vary with
|
|
|
|
* different timer clock sources, MCU-specific timer configuration, and
|
|
|
|
* board-specific clock configuration. The correct input clock frequency
|
|
|
|
* must be defined in the board.h header file.
|
|
|
|
*/
|
|
|
|
|
|
|
|
switch (((struct stm32_tim_priv_s *)dev)->base)
|
2016-06-03 17:41:17 +02:00
|
|
|
{
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM1
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM1_BASE:
|
|
|
|
freqin = BOARD_TIM1_FREQUENCY;
|
|
|
|
break;
|
2016-06-03 16:45:22 +02:00
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM2
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
freqin = BOARD_TIM2_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM3
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM3_BASE:
|
|
|
|
freqin = BOARD_TIM3_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM4
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM4_BASE:
|
|
|
|
freqin = BOARD_TIM4_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM5
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
freqin = BOARD_TIM5_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM6
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM6_BASE:
|
|
|
|
freqin = BOARD_TIM6_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM7
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM7_BASE:
|
|
|
|
freqin = BOARD_TIM7_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM8
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM8_BASE:
|
|
|
|
freqin = BOARD_TIM8_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM9
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM9_BASE:
|
|
|
|
freqin = BOARD_TIM9_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM10
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM10_BASE:
|
|
|
|
freqin = BOARD_TIM10_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM11
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM11_BASE:
|
|
|
|
freqin = BOARD_TIM11_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM12
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM12_BASE:
|
|
|
|
freqin = BOARD_TIM12_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM13
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM13_BASE:
|
|
|
|
freqin = BOARD_TIM13_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM14
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM14_BASE:
|
|
|
|
freqin = BOARD_TIM14_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM15
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM15_BASE:
|
|
|
|
freqin = BOARD_TIM15_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM16
|
2016-06-03 19:38:59 +02:00
|
|
|
case STM32_TIM16_BASE:
|
2016-06-03 20:11:55 +02:00
|
|
|
freqin = BOARD_TIM16_FREQUENCY;
|
2016-06-03 19:38:59 +02:00
|
|
|
break;
|
|
|
|
#endif
|
2016-06-03 22:17:18 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM17
|
2016-06-03 22:08:28 +02:00
|
|
|
case STM32_TIM17_BASE:
|
|
|
|
freqin = BOARD_TIM17_FREQUENCY;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2016-06-03 19:38:59 +02:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
2016-06-03 17:41:17 +02:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
2016-06-03 19:38:59 +02:00
|
|
|
/* Select a pre-scaler value for this timer using the input clock
|
|
|
|
* frequency.
|
|
|
|
*/
|
|
|
|
|
|
|
|
prescaler = freqin / freq;
|
|
|
|
|
|
|
|
/* We need to decrement value for '1', but only, if that will not to
|
|
|
|
* cause underflow.
|
2012-01-13 03:49:10 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
if (prescaler > 0)
|
|
|
|
{
|
|
|
|
prescaler--;
|
|
|
|
}
|
|
|
|
|
2016-06-03 19:38:59 +02:00
|
|
|
/* Check for overflow as well. */
|
|
|
|
|
2012-01-13 03:49:10 +01:00
|
|
|
if (prescaler > 0xffff)
|
|
|
|
{
|
|
|
|
prescaler = 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler);
|
|
|
|
stm32_tim_enable(dev);
|
|
|
|
|
|
|
|
return prescaler;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_setperiod
|
|
|
|
************************************************************************************/
|
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
|
|
|
|
uint32_t period)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_getcounter
|
|
|
|
************************************************************************************/
|
|
|
|
|
2016-07-06 20:48:30 +02:00
|
|
|
static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
return stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET);
|
|
|
|
}
|
|
|
|
|
2017-05-08 20:33:15 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_getwidth
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev)
|
|
|
|
{
|
|
|
|
/* Only TIM2 and TIM5 timers may be 32-bits in width
|
|
|
|
*
|
|
|
|
* Reference Table 2 of en.DM00042534.pdf
|
|
|
|
*/
|
|
|
|
|
|
|
|
switch (((struct stm32_tim_priv_s *)dev)->base)
|
|
|
|
{
|
|
|
|
/* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */
|
|
|
|
|
|
|
|
#if defined(CONFIG_STM32_TIM2) && !defined(STM32_STM32F10XX) && \
|
|
|
|
!defined(STM32_STM32L15XX)
|
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
return 32;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* TIM5 is 32-bits on all except F10x lines */
|
|
|
|
|
|
|
|
#if defined(CONFIG_STM32_TIM5) && !defined(STM32_STM32F10XX)
|
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
return 32;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* All others are 16-bit times */
|
|
|
|
|
|
|
|
default:
|
|
|
|
return 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_setchannel
|
|
|
|
************************************************************************************/
|
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
|
|
|
|
stm32_tim_channel_t mode)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2014-02-18 20:50:46 +01:00
|
|
|
uint16_t ccmr_orig = 0;
|
|
|
|
uint16_t ccmr_val = 0;
|
|
|
|
uint16_t ccmr_mask = 0xff;
|
|
|
|
uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
|
2012-01-13 03:49:10 +01:00
|
|
|
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
|
|
|
|
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Further we use range as 0..3; if channel=0 it will also overflow here */
|
|
|
|
|
2016-05-12 01:42:59 +02:00
|
|
|
if (--channel > 4)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2016-05-12 01:42:59 +02:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Assume that channel is disabled and polarity is active high */
|
|
|
|
|
|
|
|
ccer_val &= ~(3 << (channel << 2));
|
|
|
|
|
|
|
|
/* This function is not supported on basic timers. To enable or
|
|
|
|
* disable it, simply set its clock to valid frequency or zero.
|
|
|
|
*/
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
#if STM32_NBTIM > 0
|
2012-01-13 03:49:10 +01:00
|
|
|
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
2012-01-13 03:49:10 +01:00
|
|
|
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 0
|
2012-01-13 03:49:10 +01:00
|
|
|
)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Decode configuration */
|
|
|
|
|
|
|
|
switch (mode & STM32_TIM_CH_MODE_MASK)
|
|
|
|
{
|
|
|
|
case STM32_TIM_CH_DISABLED:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_CH_OUTPWM:
|
|
|
|
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
|
|
|
|
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Set polarity */
|
|
|
|
|
|
|
|
if (mode & STM32_TIM_CH_POLARITY_NEG)
|
|
|
|
{
|
|
|
|
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Define its position (shift) and get register offset */
|
|
|
|
|
|
|
|
if (channel & 1)
|
|
|
|
{
|
2014-02-18 20:50:46 +01:00
|
|
|
ccmr_val <<= 8;
|
|
|
|
ccmr_mask <<= 8;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (channel > 1)
|
|
|
|
{
|
|
|
|
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
|
|
|
|
}
|
|
|
|
|
2014-02-18 20:50:46 +01:00
|
|
|
ccmr_orig = stm32_getreg16(dev, ccmr_offset);
|
|
|
|
ccmr_orig &= ~ccmr_mask;
|
|
|
|
ccmr_orig |= ccmr_val;
|
|
|
|
stm32_putreg16(dev, ccmr_offset, ccmr_orig);
|
2012-01-13 03:49:10 +01:00
|
|
|
stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
|
|
|
|
|
|
|
|
/* set GPIO */
|
|
|
|
|
|
|
|
switch (((struct stm32_tim_priv_s *)dev)->base)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM1
|
|
|
|
case STM32_TIM1_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM1_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM1_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM1_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM1_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM2
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
2012-01-08 01:44:41 +01:00
|
|
|
#if defined(GPIO_TIM2_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM2_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM2_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM2_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM3
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM3_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
2012-01-08 01:44:41 +01:00
|
|
|
#if defined(GPIO_TIM3_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM3_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM3_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM3_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM4
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM4_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
2012-01-08 01:44:41 +01:00
|
|
|
#if defined(GPIO_TIM4_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM4_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM4_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM4_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-05-12 01:42:59 +02:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM5
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
2012-01-08 01:44:41 +01:00
|
|
|
#if defined(GPIO_TIM5_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM5_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM5_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM5_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-05-12 01:42:59 +02:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM8
|
|
|
|
case STM32_TIM8_BASE:
|
2012-01-13 03:49:10 +01:00
|
|
|
switch (channel)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM8_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM8_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM8_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM8_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-05-12 01:42:59 +02:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM9
|
|
|
|
case STM32_TIM9_BASE:
|
2012-01-13 03:49:10 +01:00
|
|
|
switch (channel)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM9_CH1OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 0:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM9_CH2OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 1:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM9_CH3OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#if defined(GPIO_TIM9_CH4OUT)
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
2016-06-03 21:51:43 +02:00
|
|
|
stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10
|
|
|
|
case STM32_TIM10_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM10_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM10_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM10_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM10_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11
|
|
|
|
case STM32_TIM11_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM11_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM11_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM11_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM11_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12
|
|
|
|
case STM32_TIM12_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM12_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM12_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM12_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM12_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13
|
|
|
|
case STM32_TIM13_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM13_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM13_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM13_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM13_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14
|
|
|
|
case STM32_TIM14_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM14_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM14_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM14_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM14_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode);
|
|
|
|
break;
|
2012-01-08 01:44:41 +01:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM15
|
|
|
|
case STM32_TIM15_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM15_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM15_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM15_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM15_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16
|
|
|
|
case STM32_TIM16_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM16_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM16_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM16_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM16_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2016-06-03 22:08:28 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17
|
|
|
|
case STM32_TIM17_BASE:
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
#if defined(GPIO_TIM17_CH1OUT)
|
|
|
|
case 0:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM17_CH2OUT)
|
|
|
|
case 1:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM17_CH3OUT)
|
|
|
|
case 2:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(GPIO_TIM17_CH4OUT)
|
|
|
|
case 3:
|
|
|
|
stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-27 21:53:36 +02:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2011-03-27 17:03:49 +02:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
return OK;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_setcompare
|
|
|
|
************************************************************************************/
|
|
|
|
|
2013-12-22 20:23:57 +01:00
|
|
|
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
|
|
|
|
uint32_t compare)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
case 1:
|
|
|
|
stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
|
|
|
|
break;
|
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
return OK;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_getcapture
|
|
|
|
************************************************************************************/
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
|
|
|
|
{
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
switch (channel)
|
|
|
|
{
|
|
|
|
case 1:
|
|
|
|
return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
|
|
|
|
case 2:
|
|
|
|
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
|
|
|
|
case 3:
|
|
|
|
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
|
|
|
|
case 4:
|
|
|
|
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2013-12-22 20:23:57 +01:00
|
|
|
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 22:24:59 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_setisr
|
|
|
|
************************************************************************************/
|
|
|
|
|
2017-02-27 14:46:36 +01:00
|
|
|
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
|
2017-03-01 15:49:14 +01:00
|
|
|
void * arg, int source)
|
2016-07-06 22:24:59 +02:00
|
|
|
{
|
|
|
|
int vectorno;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
DEBUGASSERT(source == 0);
|
|
|
|
|
|
|
|
switch (((struct stm32_tim_priv_s *)dev)->base)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_STM32_TIM1
|
|
|
|
case STM32_TIM1_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM1UP;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM2
|
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM2;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM3
|
|
|
|
case STM32_TIM3_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM3;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM4
|
|
|
|
case STM32_TIM4_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM4;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM5
|
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM5;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM6
|
|
|
|
case STM32_TIM6_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM6;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM7
|
|
|
|
case STM32_TIM7_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM7;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM8
|
|
|
|
case STM32_TIM8_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM8UP;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM9
|
|
|
|
case STM32_TIM9_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM9;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10
|
|
|
|
case STM32_TIM10_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM10;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11
|
|
|
|
case STM32_TIM11_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM11;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12
|
|
|
|
case STM32_TIM12_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM12;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13
|
|
|
|
case STM32_TIM13_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM13;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14
|
|
|
|
case STM32_TIM14_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM14;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15
|
|
|
|
case STM32_TIM15_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM15;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16
|
|
|
|
case STM32_TIM16_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM16;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17
|
|
|
|
case STM32_TIM17_BASE:
|
|
|
|
vectorno = STM32_IRQ_TIM17;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable interrupt when callback is removed */
|
|
|
|
|
|
|
|
if (!handler)
|
|
|
|
{
|
|
|
|
up_disable_irq(vectorno);
|
|
|
|
irq_detach(vectorno);
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise set callback and enable interrupt */
|
|
|
|
|
2017-03-01 15:49:14 +01:00
|
|
|
irq_attach(vectorno, handler ,arg);
|
2016-07-06 22:24:59 +02:00
|
|
|
up_enable_irq(vectorno);
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_IRQPRIO
|
|
|
|
/* Set the interrupt priority */
|
|
|
|
|
|
|
|
up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_enableint
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_disableint
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_ackint
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_checkint
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET);
|
|
|
|
return (regval & ATIM_SR_UIF) ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
/************************************************************************************
|
2016-07-06 21:36:17 +02:00
|
|
|
* Pubic Functions
|
2011-03-26 02:04:10 +01:00
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
/************************************************************************************
|
2016-07-06 21:36:17 +02:00
|
|
|
* Name: stm32_tim_init
|
2011-03-26 02:04:10 +01:00
|
|
|
************************************************************************************/
|
|
|
|
|
2012-01-13 03:49:10 +01:00
|
|
|
FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
|
2011-03-26 02:04:10 +01:00
|
|
|
{
|
2012-01-13 03:49:10 +01:00
|
|
|
struct stm32_tim_dev_s *dev = NULL;
|
|
|
|
|
|
|
|
/* Get structure and enable power */
|
|
|
|
|
|
|
|
switch (timer)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM1
|
|
|
|
case 1:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
|
|
|
|
break;
|
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM2
|
2012-01-13 03:49:10 +01:00
|
|
|
case 2:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM3
|
2012-01-13 03:49:10 +01:00
|
|
|
case 3:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM4
|
2012-01-13 03:49:10 +01:00
|
|
|
case 4:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM5
|
2012-01-13 03:49:10 +01:00
|
|
|
case 5:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM6
|
2012-01-13 03:49:10 +01:00
|
|
|
case 6:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM7
|
2012-01-13 03:49:10 +01:00
|
|
|
case 7:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM8
|
2012-01-13 03:49:10 +01:00
|
|
|
case 8:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM9
|
|
|
|
case 9:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10
|
|
|
|
case 10:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11
|
|
|
|
case 11:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12
|
|
|
|
case 12:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13
|
|
|
|
case 13:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14
|
|
|
|
case 14:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15
|
|
|
|
case 15:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16
|
|
|
|
case 16:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
|
|
|
|
break;
|
2016-06-03 22:08:28 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17
|
|
|
|
case 17:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
|
|
|
|
break;
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2011-03-26 02:04:10 +01:00
|
|
|
return NULL;
|
2012-01-13 03:49:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Is device already allocated */
|
|
|
|
|
|
|
|
if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
stm32_tim_reset(dev);
|
|
|
|
|
|
|
|
return dev;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
|
|
|
|
2016-07-06 21:36:17 +02:00
|
|
|
/************************************************************************************
|
|
|
|
* Name: stm32_tim_deinit
|
|
|
|
*
|
|
|
|
* TODO: Detach interrupts, and close down all TIM Channels
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
2011-03-26 02:04:10 +01:00
|
|
|
|
|
|
|
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
|
|
|
|
{
|
2016-06-03 22:49:05 +02:00
|
|
|
DEBUGASSERT(dev != NULL);
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Disable power */
|
|
|
|
|
|
|
|
switch (((struct stm32_tim_priv_s *)dev)->base)
|
|
|
|
{
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM1
|
|
|
|
case STM32_TIM1_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM2
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM3
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM3_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM4
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM4_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM5
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM6
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM6_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM7
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM7_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2015-09-01 15:52:32 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM8
|
2012-01-13 03:49:10 +01:00
|
|
|
case STM32_TIM8_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2016-06-03 21:51:43 +02:00
|
|
|
#ifdef CONFIG_STM32_TIM9
|
|
|
|
case STM32_TIM9_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10
|
|
|
|
case STM32_TIM10_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11
|
|
|
|
case STM32_TIM11_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12
|
|
|
|
case STM32_TIM12_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13
|
|
|
|
case STM32_TIM13_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14
|
|
|
|
case STM32_TIM14_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15
|
|
|
|
case STM32_TIM15_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16
|
|
|
|
case STM32_TIM16_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
|
|
|
|
break;
|
2016-06-03 22:08:28 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17
|
|
|
|
case STM32_TIM17_BASE:
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
|
|
|
|
break;
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
2012-01-13 03:49:10 +01:00
|
|
|
default:
|
2016-06-03 21:51:43 +02:00
|
|
|
return -EINVAL;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2012-01-13 03:49:10 +01:00
|
|
|
|
|
|
|
/* Mark it as free */
|
|
|
|
|
|
|
|
((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
|
|
|
|
|
|
|
|
return OK;
|
2011-03-26 02:04:10 +01:00
|
|
|
}
|
2011-03-27 21:53:36 +02:00
|
|
|
|
2016-06-03 22:08:28 +02:00
|
|
|
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */
|