2011-06-08 21:10:47 +00:00
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/****************************************************************************
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* arch/avr/src/atmega/atmega_serial.c
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*
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2012-02-11 03:50:52 +00:00
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2011-06-08 21:10:47 +00:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "atmega_config.h"
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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#include <semaphore.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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2012-03-21 19:47:23 +00:00
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#include <nuttx/serial/serial.h>
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2011-06-11 01:40:25 +00:00
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#include <avr/io.h>
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2011-06-08 21:10:47 +00:00
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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2015-12-29 18:07:11 -06:00
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#include "atmega.h"
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2011-06-08 21:10:47 +00:00
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/****************************************************************************
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2015-04-08 08:04:12 -06:00
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* Pre-processor Definitions
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2011-06-08 21:10:47 +00:00
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****************************************************************************/
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/* Some sanity checks *******************************************************/
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/* Is there at least one USART enabled and configured as a RS-232 device? */
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#ifndef HAVE_USART_DEVICE
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# warning "No USARTs enabled as RS-232 devices"
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#endif
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/* If we are not using the serial driver for the console, then we still must
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* provide some minimal implementation of up_putc.
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*/
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2012-02-11 03:50:52 +00:00
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#ifdef USE_SERIALDRIVER
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2011-06-08 21:10:47 +00:00
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/* Which USART with be tty0/console and which tty1? */
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2016-01-16 14:38:28 -06:00
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#undef CONSOLE_DEV
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#undef TTYS0_DEV
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#undef TTYS1_DEV
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2011-06-08 21:10:47 +00:00
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#if defined(CONFIG_USART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_usart0port /* USART0 is console */
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# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
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2011-06-11 00:48:01 +00:00
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# ifdef CONFIG_AVR_USART1
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2011-06-08 21:10:47 +00:00
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# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */
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# endif
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#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_usart1port /* USART1 is console */
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# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */
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2011-06-11 00:48:01 +00:00
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# ifdef CONFIG_AVR_USART0
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2011-06-08 21:10:47 +00:00
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# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */
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# endif
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2016-01-16 14:38:28 -06:00
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#elif defined(CONFIG_AVR_USART0)
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# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
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# ifdef CONFIG_AVR_USART1
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# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */
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# endif
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#elif defined(CONFIG_AVR_USART1)
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# define TTYS0_DEV g_usart1port /* USART1 is ttyS1 */
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2011-06-08 21:10:47 +00:00
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#endif
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART0
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static int usart0_setup(struct uart_dev_s *dev);
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static void usart0_shutdown(struct uart_dev_s *dev);
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static int usart0_attach(struct uart_dev_s *dev);
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static void usart0_detach(struct uart_dev_s *dev);
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2011-06-11 16:45:31 +00:00
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static int usart0_rxinterrupt(int irq, void *context);
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static int usart0_txinterrupt(int irq, void *context);
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2011-06-11 00:48:01 +00:00
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static int usart0_ioctl(struct file *filep, int cmd, unsigned long arg);
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2011-06-11 16:45:31 +00:00
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static int usart0_receive(struct uart_dev_s *dev, FAR unsigned int *status);
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2011-06-11 00:48:01 +00:00
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static void usart0_rxint(struct uart_dev_s *dev, bool enable);
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static bool usart0_rxavailable(struct uart_dev_s *dev);
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static void usart0_send(struct uart_dev_s *dev, int ch);
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static void usart0_txint(struct uart_dev_s *dev, bool enable);
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static bool usart0_txready(struct uart_dev_s *dev);
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2011-06-17 18:22:23 +00:00
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static bool usart0_txempty(struct uart_dev_s *dev);
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2011-06-11 00:48:01 +00:00
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#endif
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#ifdef CONFIG_AVR_USART1
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static int usart1_setup(struct uart_dev_s *dev);
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static void usart1_shutdown(struct uart_dev_s *dev);
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static int usart1_attach(struct uart_dev_s *dev);
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static void usart1_detach(struct uart_dev_s *dev);
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2011-06-11 16:45:31 +00:00
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static int usart1_rxinterrupt(int irq, void *context);
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static int usart1_txinterrupt(int irq, void *context);
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2011-06-11 00:48:01 +00:00
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static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg);
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2011-06-11 16:45:31 +00:00
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static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status);
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2011-06-11 00:48:01 +00:00
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static void usart1_rxint(struct uart_dev_s *dev, bool enable);
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static bool usart1_rxavailable(struct uart_dev_s *dev);
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static void usart1_send(struct uart_dev_s *dev, int ch);
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static void usart1_txint(struct uart_dev_s *dev, bool enable);
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static bool usart1_txready(struct uart_dev_s *dev);
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2011-06-17 18:22:23 +00:00
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static bool usart1_txempty(struct uart_dev_s *dev);
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2011-06-11 00:48:01 +00:00
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#endif
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2011-06-08 21:10:47 +00:00
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/****************************************************************************
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* Private Variables
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****************************************************************************/
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2011-06-11 00:48:01 +00:00
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/* USART0 operations */
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#ifdef CONFIG_AVR_USART0
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struct uart_ops_s g_usart0_ops =
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{
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.setup = usart0_setup,
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.shutdown = usart0_shutdown,
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.attach = usart0_attach,
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.detach = usart0_detach,
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.ioctl = usart0_ioctl,
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.receive = usart0_receive,
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.rxint = usart0_rxint,
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.rxavailable = usart0_rxavailable,
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2014-05-08 09:00:33 -06:00
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rxflowcontrol = NULL,
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#endif
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2011-06-11 00:48:01 +00:00
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.send = usart0_send,
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.txint = usart0_txint,
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.txready = usart0_txready,
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2011-06-17 18:22:23 +00:00
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.txempty = usart0_txempty,
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2011-06-08 21:10:47 +00:00
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};
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2011-06-11 00:48:01 +00:00
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/* USART0 I/O buffers */
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2011-06-08 21:10:47 +00:00
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static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
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static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
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2011-06-11 00:48:01 +00:00
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/* This describes the state of the ATMega USART0 port. */
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2011-06-08 21:10:47 +00:00
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static uart_dev_t g_usart0port =
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{
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.recv =
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{
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.size = CONFIG_USART0_RXBUFSIZE,
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.buffer = g_usart0rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_USART0_TXBUFSIZE,
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.buffer = g_usart0txbuffer,
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},
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2011-06-11 00:48:01 +00:00
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.ops = &g_usart0_ops,
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2011-06-08 21:10:47 +00:00
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};
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#endif
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2011-06-11 00:48:01 +00:00
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/* USART1 operations */
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2011-06-08 21:10:47 +00:00
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART1
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struct uart_ops_s g_usart1_ops =
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2011-06-08 21:10:47 +00:00
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{
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2011-06-11 00:48:01 +00:00
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.setup = usart1_setup,
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.shutdown = usart1_shutdown,
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.attach = usart1_attach,
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.detach = usart1_detach,
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.ioctl = usart1_ioctl,
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.receive = usart1_receive,
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.rxint = usart1_rxint,
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.rxavailable = usart1_rxavailable,
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.send = usart1_send,
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.txint = usart1_txint,
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.txready = usart1_txready,
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2011-06-17 18:22:23 +00:00
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.txempty = usart1_txempty,
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2011-06-08 21:10:47 +00:00
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};
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2011-06-11 00:48:01 +00:00
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/* USART 1 I/O buffers */
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static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
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static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
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/* This describes the state of the ATMega USART1 port. */
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2011-06-08 21:10:47 +00:00
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static uart_dev_t g_usart1port =
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{
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.recv =
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{
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.size = CONFIG_USART1_RXBUFSIZE,
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.buffer = g_usart1rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_USART1_TXBUFSIZE,
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.buffer = g_usart1txbuffer,
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},
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2011-06-11 00:48:01 +00:00
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.ops = &g_usart1_ops,
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2011-06-08 21:10:47 +00:00
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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2011-06-11 00:48:01 +00:00
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* Name: usart0/1_restoreusartint
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2011-06-08 21:10:47 +00:00
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****************************************************************************/
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART0
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static void usart0_restoreusartint(uint8_t imr)
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2011-06-08 21:10:47 +00:00
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{
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2011-06-11 16:45:31 +00:00
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uint8_t regval;
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regval = UCSR0B;
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regval &= ~((1 << RXCIE0) | (1 << TXCIE0) | (1 << UDRIE0));
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imr &= ((1 << RXCIE0) | (1 << TXCIE0) | (1 << UDRIE0));
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regval |= imr;
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UCSR0B = regval;
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2011-06-08 21:10:47 +00:00
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}
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2011-06-11 00:48:01 +00:00
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#endif
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2011-06-08 21:10:47 +00:00
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART1
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static void usart1_restoreusartint(uint8_t imr)
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2011-06-08 21:10:47 +00:00
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{
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2011-06-11 16:45:31 +00:00
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uint8_t regval;
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regval = UCSR1B;
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regval &= ~((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
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imr &= ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
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regval |= imr;
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UCSR1B = regval;
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2011-06-08 21:10:47 +00:00
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}
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2011-06-11 00:48:01 +00:00
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#endif
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2011-06-08 21:10:47 +00:00
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/****************************************************************************
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2011-06-11 00:48:01 +00:00
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* Name: usart0/1_disableusartint
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2011-06-08 21:10:47 +00:00
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****************************************************************************/
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART0
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static inline void usart0_disableusartint(uint8_t *imr)
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2011-06-08 21:10:47 +00:00
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{
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2011-06-17 18:22:23 +00:00
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uint8_t regval;
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regval = UCSR0B;
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2011-06-11 16:45:31 +00:00
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*imr = regval;
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regval &= ~((1 << RXCIE0) | (1 << TXCIE0) | (1 << UDRIE0));
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2011-06-17 18:22:23 +00:00
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UCSR0B = regval;
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2011-06-08 21:10:47 +00:00
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}
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2011-06-11 00:48:01 +00:00
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#endif
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2011-06-08 21:10:47 +00:00
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2011-06-11 00:48:01 +00:00
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#ifdef CONFIG_AVR_USART1
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static inline void usart1_disableusartint(uint8_t *imr)
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2011-06-08 21:10:47 +00:00
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{
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2011-06-17 18:22:23 +00:00
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uint8_t regval;
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regval = UCSR1B;
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2011-06-11 16:45:31 +00:00
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*imr = regval;
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regval &= ~((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
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2011-06-17 18:22:23 +00:00
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UCSR0B = regval;
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2011-06-08 21:10:47 +00:00
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}
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2011-06-11 00:48:01 +00:00
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#endif
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2011-06-08 21:10:47 +00:00
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/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_setup
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the USART baud, bits, parity, etc. This method is called the
|
|
|
|
* first time that the serial port is opened.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static int usart0_setup(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
|
|
|
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
2011-06-11 00:48:01 +00:00
|
|
|
/* Configure the USART as an RS-232 UART */
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
usart0_configure();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static int usart1_setup(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
2011-06-08 21:10:47 +00:00
|
|
|
/* Configure the USART as an RS-232 UART */
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
usart1_configure();
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_shutdown
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Disable the USART. This method is called when the serial
|
|
|
|
* port is closed
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static void usart0_shutdown(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 00:48:01 +00:00
|
|
|
/* Reset, disable interrupts, and disable Rx and Tx */
|
|
|
|
|
|
|
|
usart0_reset();
|
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static void usart1_shutdown(struct uart_dev_s *dev)
|
|
|
|
{
|
2011-06-08 21:10:47 +00:00
|
|
|
/* Reset, disable interrupts, and disable Rx and Tx */
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
usart1_reset();
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_attach
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the USART to operation in interrupt driven mode. This method is
|
|
|
|
* called when the serial port is opened. Normally, this is just after the
|
|
|
|
* the setup() method is called, however, the serial console may operate in
|
|
|
|
* a non-interrupt driven mode during the boot phase.
|
|
|
|
*
|
|
|
|
* RX and TX interrupts are not enabled when by the attach method (unless the
|
|
|
|
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
|
|
|
* interrupts are not enabled until the txint() and rxint() methods are called.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static int usart0_attach(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Attach the USART0 IRQs:
|
|
|
|
*
|
|
|
|
* RX: USART Receive Complete. Set when are unread data in the receive
|
|
|
|
* buffer and cleared when the receive buffer is empty.
|
|
|
|
* TX: USART Transmit Complete. Set when the entire frame in the Transmit
|
|
|
|
* Shift Register has been shifted out and there are no new data
|
|
|
|
* currently present in the transmit buffer.
|
|
|
|
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready
|
|
|
|
* to receive new data: The buffer is empty, and therefore ready to be
|
|
|
|
* written.
|
|
|
|
*/
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
(void)irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt);
|
|
|
|
(void)irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt);
|
2015-10-07 16:24:54 -06:00
|
|
|
//(void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt);
|
2011-06-11 16:45:31 +00:00
|
|
|
return OK;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static int usart1_attach(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
/* Attach the USART1 IRQs:
|
|
|
|
*
|
|
|
|
* RX: USART Receive Complete. Set when are unread data in the receive
|
|
|
|
* buffer and cleared when the receive buffer is empty.
|
|
|
|
* TX: USART Transmit Complete. Set when the entire frame in the Transmit
|
|
|
|
* Shift Register has been shifted out and there are no new data
|
|
|
|
* currently present in the transmit buffer.
|
|
|
|
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready
|
|
|
|
* to receive new data: The buffer is empty, and therefore ready to be
|
|
|
|
* written.
|
|
|
|
*/
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
(void)irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt);
|
|
|
|
(void)irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt);
|
2015-10-07 16:24:54 -06:00
|
|
|
//(void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt);
|
2011-06-11 16:45:31 +00:00
|
|
|
return OK;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_detach
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Detach USART interrupts. This method is called when the serial port is
|
|
|
|
* closed normally just before the shutdown method is called. The exception
|
|
|
|
* is the serial console which is never shutdown.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static void usart0_detach(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 00:48:01 +00:00
|
|
|
/* Disable all USART0 interrupts */
|
2011-06-11 16:45:31 +00:00
|
|
|
|
|
|
|
usart0_disableusartint(NULL);
|
2011-06-11 00:48:01 +00:00
|
|
|
|
|
|
|
/* Detach the USART0 IRQs */
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
(void)irq_detach(ATMEGA_IRQ_U0RX);
|
|
|
|
(void)irq_detach(ATMEGA_IRQ_U0DRE);
|
|
|
|
// (void)irq_detach(ATMEGA_IRQ_U0TX);
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static void usart1_detach(struct uart_dev_s *dev)
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Disable all USART1 interrupts */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
usart1_disableusartint(NULL);
|
|
|
|
|
|
|
|
/* Detach the USART1 IRQs */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
(void)irq_detach(ATMEGA_IRQ_U1RX);
|
|
|
|
(void)irq_detach(ATMEGA_IRQ_U1DRE);
|
2015-10-07 16:24:54 -06:00
|
|
|
//(void)irq_detach(ATMEGA_IRQ_U1TX);
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 16:45:31 +00:00
|
|
|
* Name: usart0/1_rxinterrupt
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
2011-06-11 16:45:31 +00:00
|
|
|
* This is the USART RX interrupt handler. It will be invoked when an
|
|
|
|
* RX interrupt received. It will call uart_receivechar to perform the RX
|
|
|
|
* data transfers.
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
2011-06-11 16:45:31 +00:00
|
|
|
static int usart0_rxinterrupt(int irq, void *context)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
uint8_t ucsr0a = UCSR0A;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Handle incoming, receive bytes (with or without timeout) */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
if ((ucsr0a & (1 << RXC0)) != 0)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2015-10-07 16:24:54 -06:00
|
|
|
/* Received data ready... process incoming bytes */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2015-10-07 16:24:54 -06:00
|
|
|
uart_recvchars(&g_usart0port);
|
2011-06-11 16:45:31 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static int usart1_rxinterrupt(int irq, void *context)
|
|
|
|
{
|
|
|
|
uint8_t ucsr1a = UCSR1A;
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Handle incoming, receive bytes (with or without timeout) */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
if ((ucsr1a & (1 << RXC1)) != 0)
|
|
|
|
{
|
2015-10-07 16:24:54 -06:00
|
|
|
/* Received data ready... process incoming bytes */
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2015-10-07 16:24:54 -06:00
|
|
|
uart_recvchars(&g_usart1port);
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 16:45:31 +00:00
|
|
|
|
|
|
|
return OK;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
2011-06-11 00:48:01 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: usart0/1_txinterrupt
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is the USART TX interrupt handler. It will be invoked when an
|
|
|
|
* TX or DRE interrupt received. It will call uart_xmitchars to perform
|
|
|
|
* the TXdata transfers.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static int usart0_txinterrupt(int irq, void *context)
|
2011-06-11 00:48:01 +00:00
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
uint8_t ucsr0a = UCSR0A;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-17 18:22:23 +00:00
|
|
|
/* Handle outgoing, transmit bytes when the transmit data buffer is empty.
|
|
|
|
* (There may still be data in the shift register).
|
|
|
|
*/
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-17 18:22:23 +00:00
|
|
|
if ((ucsr0a & (1 << UDRE0)) != 0)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2015-10-07 16:24:54 -06:00
|
|
|
/* Transmit data regiser empty ... process outgoing bytes */
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2015-10-07 16:24:54 -06:00
|
|
|
uart_xmitchars(&g_usart0port);
|
2011-06-11 16:45:31 +00:00
|
|
|
}
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static int usart1_txinterrupt(int irq, void *context)
|
|
|
|
{
|
|
|
|
uint8_t ucsr1a = UCSR1A;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-17 18:22:23 +00:00
|
|
|
/* Handle outgoing, transmit bytes when the transmit data buffer is empty.
|
|
|
|
* (There may still be data in the shift register).
|
|
|
|
*/
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-17 18:22:23 +00:00
|
|
|
if ((ucsr1a & (1 << UDRE1)) != 0)
|
2011-06-11 16:45:31 +00:00
|
|
|
{
|
2015-10-07 16:24:54 -06:00
|
|
|
/* Transmit data regiser empty ... process outgoing bytes */
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2015-10-07 16:24:54 -06:00
|
|
|
uart_xmitchars(&g_usart1port);
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 16:45:31 +00:00
|
|
|
|
|
|
|
return OK;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_ioctl
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* All ioctl calls will be routed through this method
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static int usart0_ioctl(struct file *filep, int cmd, unsigned long arg)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2016-01-08 11:21:53 -06:00
|
|
|
#ifdef CONFIG_SERIAL_TERMIOS
|
2011-06-11 00:48:01 +00:00
|
|
|
int ret = OK;
|
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
2015-12-29 17:56:44 +02:00
|
|
|
case TCGETS:
|
|
|
|
case TCSETS:
|
2011-06-11 00:48:01 +00:00
|
|
|
break;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
default:
|
|
|
|
ret = -ENOTTY;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
#else
|
|
|
|
return -ENOTTY;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg)
|
|
|
|
{
|
2016-01-08 11:21:53 -06:00
|
|
|
#ifdef CONFIG_SERIAL_TERMIOS
|
2011-06-11 00:48:01 +00:00
|
|
|
int ret = OK;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
2015-12-29 17:56:44 +02:00
|
|
|
case TCGETS:
|
|
|
|
case TCSETS:
|
2011-06-08 21:10:47 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ret = -ENOTTY;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
#else
|
|
|
|
return -ENOTTY;
|
|
|
|
#endif
|
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_receive
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Called (usually) from the interrupt level to receive one
|
|
|
|
* character from the USART. Error bits associated with the
|
|
|
|
* receipt are provided in the return 'status'.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
2011-06-11 16:45:31 +00:00
|
|
|
static int usart0_receive(struct uart_dev_s *dev, FAR unsigned int *status)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 00:48:01 +00:00
|
|
|
/* Return status information */
|
|
|
|
|
|
|
|
if (status)
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
*status = (FAR unsigned int)UCSR0A;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
/* Then return the actual received byte */
|
|
|
|
|
2011-06-11 01:40:25 +00:00
|
|
|
return UDR0;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
2011-06-11 16:45:31 +00:00
|
|
|
static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status)
|
2011-06-11 00:48:01 +00:00
|
|
|
{
|
2011-06-08 21:10:47 +00:00
|
|
|
/* Return status information */
|
|
|
|
|
|
|
|
if (status)
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
*status = (FAR unsigned int)UCSR1A;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Then return the actual received byte */
|
|
|
|
|
2011-06-11 01:40:25 +00:00
|
|
|
return UDR1;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_rxint
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable RX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static void usart0_rxint(struct uart_dev_s *dev, bool enable)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Enable/disable RX interrupts:
|
|
|
|
*
|
|
|
|
* RX: USART Receive Complete. Set when are unread data in the receive
|
|
|
|
* buffer and cleared when the receive buffer is empty.
|
|
|
|
*/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR0B |= (1 << RXCIE0);
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR0B &= ~(1 << RXCIE0);
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static void usart1_rxint(struct uart_dev_s *dev, bool enable)
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Enable/disable RX interrupts:
|
|
|
|
*
|
|
|
|
* RX: USART Receive Complete. Set when are unread data in the receive
|
|
|
|
* buffer and cleared when the receive buffer is empty.
|
|
|
|
*/
|
|
|
|
|
2011-06-08 21:10:47 +00:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR1B |= (1 << RXCIE1);
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR1B &= ~(1 << RXCIE1);
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_rxavailable
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the receive register is not empty
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static bool usart0_rxavailable(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
return (UCSR0A & (1 << RXC0)) != 0;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static bool usart1_rxavailable(struct uart_dev_s *dev)
|
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
return (UCSR1A & (1 << RXC1)) != 0;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_send
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This method will send one byte on the USART.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static void usart0_send(struct uart_dev_s *dev, int ch)
|
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
UDR0 = ch;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static void usart1_send(struct uart_dev_s *dev, int ch)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
UDR1 = ch;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_txint
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable TX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static void usart0_txint(struct uart_dev_s *dev, bool enable)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Enable/disable TX interrupts:
|
|
|
|
*
|
|
|
|
* TX: USART Transmit Complete. Set when the entire frame in the Transmit
|
|
|
|
* Shift Register has been shifted out and there are no new data
|
|
|
|
* currently present in the transmit buffer.
|
|
|
|
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready
|
|
|
|
* to receive new data: The buffer is empty, and therefore ready to be
|
|
|
|
* written.
|
|
|
|
*/
|
|
|
|
|
2016-02-13 19:11:09 -06:00
|
|
|
flags = enter_critical_section();
|
2011-06-11 00:48:01 +00:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
/* Set to receive an interrupt when the TX data register is empty */
|
|
|
|
|
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR0B |= (1 << UDRIE0);
|
|
|
|
// UCSR0B |= (1 << TXCIE0);
|
2011-06-11 00:48:01 +00:00
|
|
|
|
|
|
|
/* Fake a TX interrupt here by just calling uart_xmitchars() with
|
|
|
|
* interrupts disabled (note this may recurse).
|
|
|
|
*/
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
uart_xmitchars(&g_usart0port);
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Disable the TX interrupt */
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR0B &= ~((1 << UDRIE0) | (1 << TXCIE0));
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
2011-06-17 18:22:23 +00:00
|
|
|
|
2016-02-13 19:11:09 -06:00
|
|
|
leave_critical_section(flags);
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static void usart1_txint(struct uart_dev_s *dev, bool enable)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
/* Enable/disable TX interrupts:
|
|
|
|
*
|
|
|
|
* TX: USART Transmit Complete. Set when the entire frame in the Transmit
|
|
|
|
* Shift Register has been shifted out and there are no new data
|
|
|
|
* currently present in the transmit buffer.
|
|
|
|
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready
|
|
|
|
* to receive new data: The buffer is empty, and therefore ready to be
|
|
|
|
* written.
|
|
|
|
*/
|
|
|
|
|
2016-02-13 19:11:09 -06:00
|
|
|
flags = enter_critical_section();
|
2011-06-08 21:10:47 +00:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
/* Set to receive an interrupt when the TX data register is empty */
|
|
|
|
|
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR1B |= (1 << UDRIE1);
|
|
|
|
// UCSR1B |= (1 << TXCIE1);
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/* Fake a TX interrupt here by just calling uart_xmitchars() with
|
|
|
|
* interrupts disabled (note this may recurse).
|
|
|
|
*/
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
uart_xmitchars(&g_usart1port);
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Disable the TX interrupt */
|
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
UCSR1B &= ~((1 << UDRIE1) | (1 << TXCIE1));
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-17 18:22:23 +00:00
|
|
|
|
2016-02-13 19:11:09 -06:00
|
|
|
leave_critical_section(flags);
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-06-11 00:48:01 +00:00
|
|
|
* Name: usart0/1_txready
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the tranmsit data register is empty
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-06-11 00:48:01 +00:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static bool usart0_txready(struct uart_dev_s *dev)
|
2011-06-08 21:10:47 +00:00
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
return (UCSR0A & (1 << UDRE0)) != 0;
|
2011-06-08 21:10:47 +00:00
|
|
|
}
|
2011-06-11 00:48:01 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static bool usart1_txready(struct uart_dev_s *dev)
|
|
|
|
{
|
2011-06-11 01:40:25 +00:00
|
|
|
return (UCSR1A & (1 << UDRE1)) != 0;
|
2011-06-11 00:48:01 +00:00
|
|
|
}
|
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-17 18:22:23 +00:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: usart0/1_txempty
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the tranmsit data register and shift reqister are both
|
|
|
|
* empty
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART0
|
|
|
|
static bool usart0_txempty(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
return (UCSR0A & (1 << TXC0)) != 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
static bool usart1_txempty(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
return (UCSR1A & (1 << TXC1)) != 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-06-08 21:10:47 +00:00
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_earlyserialinit
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Performs the low level USART initialization early in debug so that the
|
|
|
|
* serial console will be available during bootup. This must be called
|
2011-06-11 00:48:01 +00:00
|
|
|
* before up_serialinit.
|
2011-06-08 21:10:47 +00:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void up_earlyserialinit(void)
|
|
|
|
{
|
|
|
|
/* Disable all USARTS */
|
|
|
|
|
2015-01-26 13:55:26 -06:00
|
|
|
#ifdef CONFIG_AVR_USART0
|
2011-06-11 16:45:31 +00:00
|
|
|
usart0_disableusartint(NULL);
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_AVR_USART1
|
|
|
|
usart1_disableusartint(NULL);
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Configuration whichever one is the console */
|
|
|
|
|
|
|
|
#ifdef HAVE_SERIAL_CONSOLE
|
|
|
|
CONSOLE_DEV.isconsole = true;
|
2011-06-11 00:48:01 +00:00
|
|
|
# if defined(CONFIG_USART0_SERIAL_CONSOLE)
|
2011-06-11 16:45:31 +00:00
|
|
|
usart0_setup(&g_usart0port);
|
2011-06-11 00:48:01 +00:00
|
|
|
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
|
2011-06-11 16:45:31 +00:00
|
|
|
usart1_setup(&g_usart1port);
|
2011-06-11 00:48:01 +00:00
|
|
|
# endif
|
2011-06-08 21:10:47 +00:00
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#endif
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}
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|
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|
|
|
|
/****************************************************************************
|
|
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|
* Name: up_serialinit
|
|
|
|
*
|
|
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|
* Description:
|
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|
* Register serial console and serial ports. This assumes
|
|
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|
* that up_earlyserialinit was called previously.
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|
*
|
|
|
|
****************************************************************************/
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|
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|
void up_serialinit(void)
|
|
|
|
{
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|
|
|
/* Register the console */
|
|
|
|
|
|
|
|
#ifdef HAVE_SERIAL_CONSOLE
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|
|
|
(void)uart_register("/dev/console", &CONSOLE_DEV);
|
|
|
|
#endif
|
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|
|
|
|
|
|
/* Register all USARTs */
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|
|
|
|
|
|
|
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
|
|
|
|
#ifdef TTYS1_DEV
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|
|
|
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
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|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_putc
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Provide priority, low-level access to support OS debug writes
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int up_putc(int ch)
|
|
|
|
{
|
|
|
|
#ifdef HAVE_SERIAL_CONSOLE
|
2011-06-11 00:48:01 +00:00
|
|
|
uint8_t imr;
|
2011-06-08 21:10:47 +00:00
|
|
|
|
2011-06-11 16:45:31 +00:00
|
|
|
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
|
|
|
|
usart0_disableusartint(&imr);
|
|
|
|
#else
|
2015-01-26 13:55:26 -06:00
|
|
|
usart1_disableusartint(&imr);
|
2011-06-11 16:45:31 +00:00
|
|
|
#endif
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/* Check for LF */
|
|
|
|
|
|
|
|
if (ch == '\n')
|
|
|
|
{
|
|
|
|
/* Add CR */
|
|
|
|
|
|
|
|
up_lowputc('\r');
|
|
|
|
}
|
|
|
|
|
|
|
|
up_lowputc(ch);
|
2011-06-11 16:45:31 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
|
|
|
|
usart0_restoreusartint(imr);
|
|
|
|
#else
|
|
|
|
usart1_restoreusartint(imr);
|
2011-06-08 21:10:47 +00:00
|
|
|
#endif
|
2011-06-11 16:45:31 +00:00
|
|
|
#endif
|
|
|
|
|
2011-06-08 21:10:47 +00:00
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
|
2012-02-11 03:50:52 +00:00
|
|
|
#else /* USE_SERIALDRIVER */
|
2011-06-08 21:10:47 +00:00
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_putc
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Provide priority, low-level access to support OS debug writes
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int up_putc(int ch)
|
|
|
|
{
|
|
|
|
#ifdef HAVE_SERIAL_CONSOLE
|
|
|
|
/* Check for LF */
|
|
|
|
|
|
|
|
if (ch == '\n')
|
|
|
|
{
|
|
|
|
/* Add CR */
|
|
|
|
|
|
|
|
up_lowputc('\r');
|
|
|
|
}
|
|
|
|
|
|
|
|
up_lowputc(ch);
|
|
|
|
#endif
|
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
|
2012-02-11 03:50:52 +00:00
|
|
|
#endif /* USE_SERIALDRIVER */
|
2011-06-08 21:10:47 +00:00
|
|
|
|