Enable CONFIG_DEV_SIMPLE_ADDRENV for all the qemu configs that used
the virtio driver to fix compile error when use the NuttX implemented
metal io read/write operations.
Becasue up_addrenv_pa_to_va() and up_addrenv_va_to_pa() are not
implemented by default.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
When I try to set priorities in certain programs, such as init_priority(HIGH_PRIORITY), I've noticed that during linking, there's no guarantee that the programs will be compiled in the sequence I've specified based on priority. This has led to some runtime errors in my program.
I realized that in the ld file, when initializing dynamic arrays, there's no assurance of initializing init_array.* before init_array. This has resulted in runtime errors in the program. Consequently, I've rearranged the init_array.* in the ld file of NuttX to be placed before init_array and added a SORT operation to init_array.* to ensure accurate initialization based on priorities during linking.
update LIBFDT to LIBC_FDT
update CONFIG_LIBFDT_DTC_VERSION to CONFIG_LIBC_FDT_DTC_VERSION
move dtc source code to fdt/dtc
move version_gen.h from apps/system/fdt to current dir
Signed-off-by: liaoao <liaoao@xiaomi.com>
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
Summary:
- I noticed that device discovery for virtio-mmio devices does not
work without bus=virtio-mmio-bus.x option. Without this option,
qemu assigns the virtio device into the virtio-mmio space
in reverse order automatically.
- To fix this issue, we must specify the correct numbers for the
target machines. (i.e. arm32/64->32, rv32/64->8)
Impact:
- None
Testing:
- Tested with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary
Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
the change do this
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Sumary
add hostfs support for arm64, it's a copy
from arm32.
Note:
it's not support for opendir and readdir, command
like ls will not work.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
(IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
support mmio transport layer, and the new framwork support
more transport layer and this commit has implemented all the
old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
configs, and update its README.txt;
New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
| | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh | 539Mbps | 524Mbps | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp | 401Mbps | 437Mbps | 583Mbps | 505Mbps |
| rv-virt:netnsh | 487Mbps | 512Mbps | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp | 387Mbps | 455Mbps | 447Mbps | 502Mbps |
| rv-virt:netnsh64 | 602Mbps | 595Mbps | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp | 414Mbps | 515Mbps | 491Mbps | 525Mbps |
| rv-virt:knetnsh64 | 515Mbps | 457Mbps | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp | 308Mbps | 389Mbps | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
Tested in QEMU 7.2.2
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
replace *(.init_array .init_array.*) with KEEP(*(.init_array .init_array.*)).
The KEEP statement within a linker script will instruct the linker to keep the specified section, even if no symbols inside it are referenced. This statement is used within the SECTIONS section of the linker script. This becomes relevant when garbage collection is performed at link time, enabled by passing the --gc-sections switch to the linker. The KEEP statement instructs the linker to use the specified section as a root node when creating a dependency graph, looking for unused sections. Essentially forcing the section to be marked as used.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
When reading https://github.com/apache/nuttx-apps/pull/1793, I found a previous problem https://github.com/apache/nuttx-apps/pull/1454#discussion_r1045718067 now still exists on current master (inf in iperf bandwidth).
By step-by-step debugging, I found a value of 1000000.0 stored in register d8 is overwritten as 0 after context switch, then fdiv results in inf because of divided by 0. Finally I found that ARCH_FPU is not enabled while compiler is using FPU, and may lose values in floating-point registers.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Summary:
- This commit adds netnsh_hv and netnsh_smp_hv to run the NuttX
with hypervisor environments
- Also updates README.txt
Impact:
- None
Testing:
- Tested with qemu=7.1 + kvm on raspi3b+ (ubuntu server 20.04)
- Tested with qemu-7.1 + hvf on M1/MBP (macOS 12.6.1)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that virtio-blk and FAT are not enabled for some
virt configurations.
- This commit enables them for testing.
Impact:
- None
Testing:
- Tested with qemu-7.1
- NOTE: file copy with rv-virt:knetnsh64 is sometimes unstable.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Currently only Port UART0 is supported for Allwinner A64. This PR adds support for all UART Ports: UART1 to UART4. (Except R-UART, which is a special low-power UART)
This is required for the upcoming LTE Modem Driver (Quectel EG25-G) for PINE64 PinePhone, which uses UART3. [(Details here)](https://lupyuen.github.io/articles/lte2)
The code was adapted from the NuttX UART Driver for Allwinner A1X: [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)
`arch/arm64/src/a64/a64_serial.c`: Added ports UART1 to UART4, based on [`a1x_serial.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_serial.c)
`arch/arm64/src/a64/a64_serial.h`: Added IRQs for UART1 to UART4. Moved UART Base Addresses to `a64_memorymap.h`
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added UART Base Addresses for UART0 to UART4
`arch/arm64/src/a64/Kconfig`: Added UART1 to UART4 to Allwinner A64 Peripheral Selection menu
`boards/arm64/a64/pinephone/configs/lcd/defconfig`, `lvgl/defconfig`, `nsh/defconfig`, `sensor/defconfig`: Fixed `UART1_SERIAL_CONSOLE` to `UART0_SERIAL_CONSOLE`
At present, the serial drivers qemu_serial.c and serial_pl011.c on the fvp-v8r and qemu platforms in arm64 are duplicated
and need to be merged. The plan is to place them under the drivers\serial directory to create a common code module,
so that both fvp-v8r and qemu can use the same code.
In the future, if new platforms use pl011 serial ports, they can also be directly reused
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
the PR submit a base method to see performance counts for
the FPU with NuttX procfs
Please read README.txt at chapter of FPU Support and Performance
for more information
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:
- GICv3 interrupt controllers for ARMv8-r
- PL011 UART controller(FVP)
Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
board readme.txt
TODO: merge PL011 UART driver to common place
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
This PR adds the existing Goodix GT9XX Touch Panel Driver to the Bringup Function for PINE64 PinePhone.
With this PR, LVGL Touchscreen Apps will respond to Touch Input on PinePhone.
### Modified Files
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Added GT9XX Touch Panel Driver to PinePhone Bringup Function
`boards/arm64/a64/pinephone/src/Makefile`: Added `pinephone_touch.c` to the Makefile
`include/nuttx/input/gt9xx.h`: Fixed a comment in GT9XX Touch Panel Driver
### New Files
`boards/arm64/a64/pinephone/src/pinephone_touch.c`, `pinephone_touch.h`: Register GT9XX Touch Panel Driver on PinePhone
`boards/arm64/a64/pinephone/configs/lvgl/defconfig`: Added PinePhone Board Config `lvgl` to support LVGL Touchscreen Apps
### Updated Documentation
`Documentation/platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Config `lvgl` for LVGL Touchscreen Apps
This PR fixes the missing pixels in the rendered output of the Frame Buffer Driver for PINE64 PinePhone.
We fix this by copying the RAM Frame Buffer to itself on Frame Buffer Update `FBIO_UPDATE`, which will refresh the display correctly over DMA / Display Engine / Timing Controller TCON0.
### Modified Files
`boards/arm64/a64/pinephone/Kconfig`: Add requirement for Frame Buffer Update `FB_UPDATE` for PinePhone LCD Display
`boards/arm64/a64/pinephone/src/pinephone_display.c`: Implement Frame Buffer Update `FBIO_UPDATE` by copying the RAM Frame Buffer to itself
This PR adds the Frame Buffer Driver for PINE64 PinePhone. With this driver, NuttX Apps will be able to use the standard Frame Buffer API to render graphics on PinePhone.
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Render Test Pattern after calling `up_fbinitialize()` to start the Frame Buffer Driver
`boards/arm64/a64/pinephone/src/pinephone_display.c`: Add Frame Buffer Driver
`boards/arm64/a64/pinephone/src/pinephone_display.h`: Declare new function for rendering Test Pattern
`platforms/arm/a64/boards/pinephone/index.rst`: Add Frame Buffer as supported driver for PinePhone
This PR adds the driver for Xingbangda XBD599 LCD Panel (based on Sitronix ST7703 LCD Controller) on PINE64 PinePhone. This PR also includes:
- The driver for X-Powers AXP803 Power Mgmt IC, which calls our driver for Allwinner A64's Reduced Serial Bus. The PMIC Driver is needed to power on the MIPI DSI Interface for the LCD Panel.
- A simple Display Driver that renders a Test Pattern on the LCD Display at startup. It calls our Allwinner A64 drivers for Display Engine, Timing Controller TCON0 and MIPI Display Serial Interface.
The NuttX Frame Buffer Driver will be implemented in the next PR.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Changed the Frame Buffer pointer to `const` for Allwinner A64 Display Engine
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for PWM, for controlling the PWM Backlight
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Call `fb_register()` to start the Display Driver at startup
`boards/arm64/a64/pinephone/src/Makefile`: Added LCD Driver, PMIC Driver and Display Driver to Makefile
`boards/arm64/a64/pinephone/Kconfig`: Added the Kconfig option for "PINE64 PinePhone > LCD Display" (`CONFIG_PINEPHONE_LCD`) which enables the LCD Driver, PMIC Driver and Display Driver
`boards/arm64/a64/pinephone/src/pinephone_lcd.c`, `pinephone_lcd.h`: Driver for Xingbangda XBD599 LCD Panel
`boards/arm64/a64/pinephone/src/pinephone_pmic.c`, `pinephone_pmic.h`: Driver for X-Powers AXP803 Power Mgmt IC
`boards/arm64/a64/pinephone/src/pinephone_display.c`: Simple Display Driver that renders a Test Pattern in `up_fbinitialize()`
`boards/arm64/a64/pinephone/configs/lcd/defconfig`: New PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver (`CONFIG_PINEPHONE_LCD`)
`platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver
This PR adds the driver for Reduced Serial Bus (RSB) on Allwinner A64 SoC. The RSB Driver will be called by the upcoming Power Mgmt IC Driver for PINE64 PinePhone, to power on the LCD Display.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > RSB" (`CONFIG_A64_RSB`), which enables the RSB Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for RSB
`arch/arm64/src/a64/Make.defs`: Added the RSB Driver to the Makefile
`arch/arm64/src/a64/a64_de.c`: Increase PLL Timeout for Allwinner A64 Display Engine
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Set PinePhone Board Config `CONFIG_BOARD_LOOPSPERMSEC` to the value computed by `calib_udelay`
`arch/arm64/src/a64/a64_rsb.c`, `a64_rsb.h`: RSB Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added RSB as supported peripheral for PinePhone
This PR adds the driver for Display Engine 2.0 on Allwinner A64 SoC. The Display Engine Driver will be called by the upcoming LCD Driver for PINE64 PinePhone.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > DE" (`CONFIG_A64_DE`), which enables the Display Engine Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for Display Engine
`arch/arm64/src/a64/Make.defs`: Added the Display Engine Driver to the Makefile
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Removed Scheduler Debug Info (`CONFIG_DEBUG_SCHED_INFO`) from the PinePhone Board Config, because it garbles the Console Output.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Display Engine Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added Display Engine as supported peripheral for PinePhone
Summary:
- This commit enables the ping command for netnsh and netnsh_smp
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This PR adds the drivers for Allwinner A64 PIO (Programmable I/O) and PinePhone LEDs (Red / Green / Blue).
The PIO Driver is based on the NuttX PIO Driver for Allwinner A10: [`arch/arm/src/a1x/a1x_pio.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_pio.c)
- `arch/arm64/src/a64/Make.defs`: Add PIO Driver to Makefile
- `boards/Kconfig`: Add `ARCH_HAVE_LEDS` to PinePhone
- `boards/arm64/a64/pinephone/src/pinephone.h`: Define PinePhone LEDs
- `boards/arm64/a64/pinephone/src/pinephone_boardinit.c`: Start Auto LEDs
- `boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Start User LEDs
- `boards/arm64/a64/pinephone/src/Makefile`: Add LED Driver to Makefile
- `boards/arm64/a64/pinephone/configs/nsh/defconfig`: Add `CONFIG_USERLED` to `nsh` config
- `arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Allwinner A64 PIO Driver
- `arch/arm64/src/a64/hardware/a64_memorymap.h`: PIO Memory Map
- `arch/arm64/src/a64/hardware/a64_pio.h`: PIO Definitions
- `boards/arm64/a64/pinephone/include/board.h`: Define PinePhone LEDs
- `boards/arm64/a64/pinephone/src/pinephone_autoleds.c`: Driver for Auto LEDs
- `boards/arm64/a64/pinephone/src/pinephone_userleds.c`: Driver for User LEDs
- `introduction/supported_platforms.rst`: Add Allwinner A64 as Supported Platform
- `platforms/arm/a64/boards/pinephone/index.rst`: Add PIO and LEDs to PinePhone
Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.
This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).
- `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.
- `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).
Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.
- `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.
- `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.
- `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.
- `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.
- `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.
- `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
This change adds the following:
- Rename the board configuration name from qemu-a53 to qemu-v8a.
- Add the configurations for Cortex-A57 and Cortex-A72.
Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
Configuring...
Building NuttX...
Normalize qemu-a53/nsh
13a14
> CONFIG_ARCH_CHIP_QEMU_A53=y
Saving the new configuration file
On branch master
Your branch is up to date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: boards/arm64/qemu/qemu-a53/configs/nsh/defconfig
modified: boards/arm64/qemu/qemu-a53/configs/nsh_smp/defconfig
retrigger ci build.
Use CONFIG_ARCH_CHIP_QEMU instead of CONFIG_ARCH_CHIP_QEMU_A53. This is because these configurations depend on the hardware configuration of qemu (memory map, irq numbers, etc.).
Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
N/A
Summary:
Arm64 support for NuttX, Features supported:
1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:
https://bugs.linaro.org/show_bug.cgi?id=5825
it's seem GCC give a wrong instruction at certain machine which
without architecture features
the new toolchain is not available still, so just disable the MACOS
cibuild check at present
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
