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2935 Commits

Author SHA1 Message Date
Gregory Nutt
736d3c169a Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined. 2014-08-06 16:26:01 -06:00
Gregory Nutt
7b9c44101d SAMA5D3 HSMCI: TX DMA is again disabled 2014-08-05 07:07:39 -06:00
Gregory Nutt
159bcc255d SAMA5 PCK: Add Main clock as an option for the PCK clock source 2014-08-03 10:17:50 -06:00
Gregory Nutt
c75bf6d741 SAMA5 SSC: Verify that the requested bit width is supported. Correct some alignment tests that depend upon the data bit width. 2014-08-02 14:26:49 -06:00
Gregory Nutt
83dab03576 SAMA5 WM8904: Fix errors in programmable clock output configuration 2014-08-01 15:18:58 -06:00
Gregory Nutt
805a02965c SAMA5 SSC: Start Delay is now configurable 2014-08-01 14:10:37 -06:00
Gregory Nutt
50bd2ba46c SAMA5 SSC: Frame Synch Delay is now configurable 2014-08-01 12:25:31 -06:00
Gregory Nutt
0b4090df0d SAMA5D SSC: Needs to account for data offset in audio buffer. 2014-07-31 19:14:24 -06:00
Gregory Nutt
c657139b30 SAMA5D3X-EK: Add support for the WM8904 audio CODEC 2014-07-31 11:14:57 -06:00
Gregory Nutt
24af676c05 SAMA5: Changes needed for a clean SAMA5D3 build after all of the recent SAMA5D4 changes. 2014-07-31 11:09:56 -06:00
Gregory Nutt
276cc44878 SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional. They are so now TX DMA is re-enabled in the driver. This might affect the SAMA5D3 platforms where the TX DMA problem was found. The SAMA4D3 and 4 use the same HSMCI driver. Much has change since then and it is not surprising that DMA is now functional. However, the has not be re-verified on the SAMA5D3 which has a different DMA controller. 2014-07-30 11:20:06 -06:00
Gregory Nutt
4df0fbec04 SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling. Interrupts were being disable so that the callbacks occurred with interrupts disabled. This resulted in loss of some interrupts and some not-so-good behaviors. The solution is to perform all callbacks on the work thread unconditionally (2014-7-29). 2014-07-30 10:19:41 -06:00
Gregory Nutt
70be3bae16 SAMA5D HSMCI: Add method to do RX transfer without DMA. The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode 2014-07-29 21:13:28 -06:00
Gregory Nutt
53930d5531 SAMA5D-EK: Correct system timer frequency. Input clock is MCK/2, not MCK 2014-07-29 07:12:36 -06:00
Gregory Nutt
1b6eec572d Cosmetic changes to comments 2014-07-29 07:11:16 -06:00
Gregory Nutt
8c2b458d75 Fixes to last SAMA5 PMIC checkin 2014-07-28 17:09:37 -06:00
Gregory Nutt
d450993f2e LPC17xx: DC updates from Max. Also fixes some syntax errors that I introduced in the last commit. 2014-07-28 07:23:49 -06:00
Gregory Nutt
100bba42be ARM: Move L2 cache initialization to much later in the sequence 2014-07-27 10:03:33 -06:00
Gregory Nutt
c523abdc62 ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly 2014-07-26 18:48:54 -06:00
Gregory Nutt
4446d6e98d ARMv7 L2 Cache: Minor bugfixes/improvements 2014-07-26 18:48:26 -06:00
Gregory Nutt
0519118de2 Enables cache early in boot-up sequence 2014-07-26 18:48:00 -06:00
Gregory Nutt
d09ee81320 Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled 2014-07-26 18:47:33 -06:00
Gregory Nutt
0d83d198de New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled 2014-07-26 18:46:52 -06:00
Gregory Nutt
ca3776a7ec Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place. 2014-07-26 16:54:19 -06:00
Gregory Nutt
ec70cfe44c arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache. 2014-07-26 16:50:08 -06:00
Gregory Nutt
be198337f7 ARMv7-A: L2CC PL310 address filtering is an optional feature 2014-07-25 19:46:09 -06:00
Gregory Nutt
ef5bfd72a6 ARMv7-A: Add missing L2CC PL310 bit definitions 2014-07-25 19:41:35 -06:00
Gregory Nutt
597c9839cc rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. 2014-07-25 17:25:17 -06:00
Gregory Nutt
47752a35c1 3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN 2014-07-24 16:51:07 -06:00
Gregory Nutt
8718dad9c8 Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT 2014-07-24 16:42:15 -06:00
Gregory Nutt
7f5b88dbcd LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max 2014-07-24 16:39:18 -06:00
Gregory Nutt
fdff663e57 Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max 2014-07-24 16:23:31 -06:00
Gregory Nutt
ab572091c5 Mostly cosmetic changes from Max 2014-07-24 16:00:21 -06:00
Gregory Nutt
ad3626e61a Eliminate warnings. From Max 2014-07-24 15:50:37 -06:00
Gregory Nutt
6dcb524d16 Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max 2014-07-24 15:37:13 -06:00
Gregory Nutt
0fcc0adaa2 Fix a recently introduced typo that was being masked by some bad conditional compilation 2014-07-22 11:45:14 -06:00
Gregory Nutt
17abe05357 Update ChangeLog 2014-07-22 07:25:01 -06:00
Gregory Nutt
3bb6a877fd STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen 2014-07-22 07:23:17 -06:00
Gregory Nutt
f76cac2773 Fix typos in the STM32 DAC header file. From Petteri Aimonen 2014-07-22 07:13:33 -06:00
Gregory Nutt
121c00036d SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this 2014-07-21 17:46:35 -06:00
Gregory Nutt
df65c5e4df SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled 2014-07-21 17:45:48 -06:00
Gregory Nutt
b9f1fbeb6c SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC 2014-07-21 16:49:56 -06:00
Gregory Nutt
f508c07b97 SAMA5 XDMAC: Missing some CUBC bits 2014-07-21 16:47:16 -06:00
Gregory Nutt
43b214addd SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete 2014-07-21 13:24:55 -06:00
Gregory Nutt
3b24da2d7c XDMAC register sampling missed CIM register; Should not set SWREQ bit in DMA setup 2014-07-21 13:23:36 -06:00
Gregory Nutt
e202c8e9b2 Fix a commented out assertion 2014-07-20 17:06:55 -06:00
Gregory Nutt
e8c030a833 Fix typos in comments 2014-07-20 13:09:47 -06:00
Gregory Nutt
7fa1eec246 SAMA5D4-EK: PIO Schmitt trigger logic backward 2014-07-20 13:04:30 -06:00
Gregory Nutt
f4bcb730d2 WM8904 w/NxPlayer: Fix some compile errors and warnings with debug enabled 2014-07-20 09:17:36 -06:00
Gregory Nutt
54d441b5c9 SAMA5D ADC: Fix some typos in conditional compilation 2014-07-19 13:56:48 -06:00