Commit Graph

250 Commits

Author SHA1 Message Date
fenghang
555d25633a add phyplus_rel_1.4
update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files
2022-02-15 10:21:10 +08:00
Michael Jung
5c1c939cdc stm32u5: Architecture Support for STM32U5
Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
chao.an
8eb999ff03 arch/arm: select ARM_THUMB by default for Cortex-M
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:30:53 -06:00
chao.an
2737701996 cortex-m/hardfault: add secure-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 07:08:13 -06:00
Juha Niskanen
422ceec99b Fix typos in comments and Kconfig files
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-21 03:26:16 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-12-11 11:32:17 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 05:36:00 -06:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
2021-12-07 01:37:29 -06:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-11-29 21:31:08 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-17 08:59:14 -03:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
David Sidrane
9d8f7126f6 armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET
When NuttX is booted from a foreign (non NuttX)
   bootloader. There as a possibility that the
   bootloader configured the MPU, in an
   incompatible way for the NuttX memory usage.

   The option to reset the MPU before it is initialized
   may not succeed if the bss and data initialization
   code violated the previous MPU configurations.

   Added herein are ARM_MPU_RESET and
   ARM_MPU_EARLY_RESET. The former can be used
   If the system is capable of booting and running
   NuttX MPU configuration code without an MPU
   violation. The latter is used if the system can
   not run the bss and data initialization code.

   These are options so that a NuttX may be configured to
   not clobber a bootloader MPU configuration in a system
   that is architected to share the MPU configuration task.
2021-10-23 03:58:26 -05:00
Xiang Xiao
850367d5bb arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-12 09:09:42 -03:00
ligd
f1aec38ffa arm: add ARM_HAVE_NEON to Kconfig
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-08-26 13:25:43 +08:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
2021-07-23 02:32:19 -07:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 07:14:17 -05:00
Masayuki Ishikawa
f0b689a063 arch: arm: Add select ARCH_HAVE_MODULE_TEXT to ARCH_CHIP_CXD56XX
Summary:
- I noticed that make savedefconfig shows warnings regarding
  'unmet direct dependencies (ARCH_HAVE_MODULE_TEXT)'
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with spresense:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-06-04 01:40:37 -05:00
chao.an
6c40185985 arm/v7-a/fpu: add VFP-v3 D32 support
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-05-21 09:55:00 -03:00
Michael Jung
f3a5675cc4 stm32l5: Architecture Support for STM32L5
Architecture support for STMicroelectronics STM32L552xx and STM32L562xx
MCUs.  This is based on corresponding code for STM32L4, but has been
considerably adjusted.  Tested with Nucleo-L552ZE-Q and STM32L562E-DK
boards with simple NSH configurations.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Masayuki Ishikawa
8085010ae8 arch: arm: Add 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040
Summary:
- This commit adds 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040
- Now NuttX spinlock uses WFE/SEV to reduce power consumption
- Also, modify a comment on rp2040

Impact:
- rp2040 only

Testing:
- Tested with raspberrypi-pico:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-24 19:12:22 -08:00
Yuichi Nakamura
01699e00e0 arm/rp2040: Raspberry Pi Pico SMP support 2021-02-25 07:20:59 +09:00
David Sidrane
62321fa5db s32k1xx:Support ramfunc 2021-02-23 18:11:41 -08:00
Yuichi Nakamura
ed1da60f52 arch/arm: Add RP2040 (Raspberry Pi Pico's SoC) support 2021-02-20 03:45:24 -08:00
Alan C. Assis
b0d611d3dc Replace ARM_LWL_CONSOLE with generic LWL_CONSOLE 2021-01-31 06:14:50 -08:00
Matias N
e5200d4af9 nrf52: add stackcheck support 2021-01-27 09:49:16 -08:00
Matias N
ebe596bcd1 nrf52: enable and fix build for SPI BITORDER 2021-01-16 21:04:44 -08:00
Masayuki Ishikawa
6158b6b77b spinlock: Introduce SP_WFE() and SP_SEV()
Summary:
- This commit introduces SP_WFE() and SP_SEV() to be used for spinlock
- Also, use wfe/sev instructions for ARMV7-A to reduce power consumption

Impact:
- ARMV7-a SMP only

Testing:
- sabre-6quad:smp (QEMU, dev board)
- maix-bit:smp, esp32-devkitc:smp, spresense:smp sim:smp (compile only)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-11 05:58:35 -06:00
liuhaitao
d5c6bfe6cf arch: Add custom arch chip build support
Just like custom board build support, add custom arch chip build
support.

Change-Id: I71c87e6b2195501a1b1d728b71d7cbe344951057
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
2020-10-20 14:48:16 +08:00
raiden00pl
35a5036e32 nrf52: add serial termios support 2020-09-30 09:09:04 -03:00
Xiang Xiao
031984f76a arch/arm: Select arm family when ARCH_ARM1136J/ARCH_ARM1156T2/ARCH_ARM1176JZ is defined
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-22 23:05:29 +01:00
Xiang Xiao
7faf72cabc arch/arm: Add ARCH_ARMV6M Kconfig to prepare the support of CortexM0+
also align with the armv7m implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-22 23:05:29 +01:00
raiden00pl
a2b00fd348 nrf52: add PWM support 2020-09-13 10:57:11 -03:00
Matias N
459ad29799 nrf52: extend systimer support; support WFI/WFE again
This commit exends systimer options for nRF52 arch. It is possible
to use ARM SysTick either for tickless or non-tickless mode. Also,
it is possible to use the RTC peripheral for tickless mode. This
also re-enables support for WFI/WFE sleep if RTC is used, since
this counter continues to run in this mode (in contrast to SysTick).
2020-09-10 12:10:20 +02:00
Masayuki Ishikawa
08c4376606 arch, include, sched : Refactor ARCH_GLOBAL_IRQDISABLE related code
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code

Impact:
- Should have no impact because the logic is the same for SMP

Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-09-03 10:20:20 +08:00
leomarradke
f5912b5cba arch: samd5e5 : Oneshot, freerun and tickless available support. All support runs on Timer/Counter (TC).
Some fixes in external interrupt controller (EIC) and clockconfig.

Testing:
- Build check only.

Signed-off-by: Leomar Mateus Radke  <leomar@falker.com.br>
2020-08-18 12:42:44 -03:00
SPRESENSE
d560ce65ff cxd56xx: spresense: Add some improvements and fix bugs for Spresense board
- Add new functions of GNSS
- Support the lower PWM frequency
- Add CONFIG_CPUFREQ_RELEASE_LOCK
- Add high speed ADC support
- Add HPADC input gain configuration
- Add eMMC device
- Frame buffer support
- Fix SD/GNSS/sensor drivers not worked
- Build errors
- Fix nxstyle issues
2020-07-28 09:13:05 +02:00
Brennan Ashton
aef6f4ae09 Add initial support for the QuickLogic EOS S3
The QuickFeather board added as an initial target.
These featrues are minimally implemented:
  * Clock Configuration -- All clocking registers are defined and
    configuration is used to setup the HSO, M4 Core, and M4 Perif
    clocks.  Additionally some clock debugging is stubbed for
    bringing out clock paths to IO pins.

  * UART -- The lowputc as well as the serial driver is implemnted
    for the single UART device. Currently the configuration is
    hard coded, but uses the proper interfaces to later fill in.

  * SysTick -- The system tick timer is implemented and clocking
    properly. Tickless mode is not yet implemented.

  * Interrupts -- The interrupt system is implemented and verified
    using the UART and SysTick systems.

  * GPIO -- GPIO and IOMUX systems are defined and implemented.
    This is verified using the UART as well as the Arch LED
    system.  The GPIO interupt system is stubbed out but not
    implemented.

  * Arch LEDS -- The blue LED as part of the RGB LED is configured
    and attached to the Arch LED system.  This indicates the device
    coming online as well as when a hardfault is triggered.

Applications and Testing:
  * There is a nsh configuration implemented that includes debug
    features as well as the ostest, getprime, and mem test.
    All of these have been run and verified.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2020-07-15 11:25:30 +01:00
Nathan Hartman
168a4cafc6 Add support for STM32G474: Modify existing files
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.

This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.

arch/arm/Kconfig:
arch/arm/include/stm32/chip.h:
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/Kconfig:
arch/arm/src/stm32/hardware/stm32_adc.h:
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
arch/arm/src/stm32/hardware/stm32_dma.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_flash.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_i2c_v2.h:
arch/arm/src/stm32/hardware/stm32_memorymap.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/hardware/stm32_tim.h:
arch/arm/src/stm32/stm32_allocateheap.c:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dma_v1.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.c:
arch/arm/src/stm32/stm32_gpio.h:
arch/arm/src/stm32/stm32_lowputc.c:
arch/arm/src/stm32/stm32_rcc.c:
arch/arm/src/stm32/stm32_rcc.h:
arch/arm/src/stm32/stm32_serial.c:
arch/arm/src/stm32/stm32_syscfg.h:
arch/arm/src/stm32/stm32_uart.h:

    * Add architectural support to existing NuttX files. This
      makes the STM32G474 family parts accessible to the system.

With big thanks for detailed code review:
    David Sidrane (davids5)
    Mateusz Szafoni (raiden00)
    Abdelatif Guettouche (Ouss4)
2020-05-23 09:02:00 -03:00
qiaowei
2376d8a266 Porting arch/armv8-m support
1. Add dsp extension; float point based on hardware and software.
2. Delete folder "iar"
3. Add tool chain for cortex-M23 and cortex-M35p

Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7
2020-04-26 07:43:37 -06:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Masayuki Ishikawa
f38f39d410 arch: arm: Select ARCH_GLOBAL_IRQDISABLE for iMX6
NOTE: SMP related behaviour will be same as armv7-m SMP

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-02-19 20:04:58 -06:00
YAMAMOTO Takashi
7513cb6921 CONFIG_ARM_SEMIHOSTING_HOSTFS: mention limited support of directories 2020-02-18 17:11:59 +08:00
David Sidrane
f506e2bd72 Merged in david_s5/nuttx/master_h7 (pull request #1058)
STM32H7:Flash driver and Serious BUG fixes.

* arch/arm/Kconfig:Add ARCH_HAVE_PROGMEM for STM32H7

* stm32h7:Add FLASH progmem support

* stm32h7:pwr add CPUCR & D3CR

* stm32h7:syscfg Add PWRCR

* stm32h7:rcc Properly configure VOS and Flash

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-10-22 19:49:49 +00:00
Masayuki Ishikawa
4c53f0d232 Merged in masayuki2009/nuttx.nuttx/spresense_smp (pull request #1041)
Spresense smp

* arch: arm: Add ARCH_GLOBAL_IRQDISABLE to ARCH_CHIP_CXD56XX in Kconfig

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch: arm: cxd56xx: Make fpuconfg() public in cxd56_start.c

    NOTE: fpuconfig() is called in both cxd56_start.c and cxd56_cpustart.c

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch: arm: cxd56xx: Add support for SMP

    NOTE: To run cxd56xx in SMP mode, new boot loader which will be
    released later must be used.

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* arch: arm: cxd56xx: Add irq routing for SMP in cxd56_irq.c

    NOTE: In cxd56xx, each external interrupt controller can be
    accessed from a local APP_DSP (Cortex-M4F) only. This commit
    supports IRQ routing for SMP by calling up_send_irqreq() in
    both up_enable_irq() and up_disable_irq().

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

* boards: spresense: Add smp configuration

    Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-10-03 13:06:21 +00:00
David Sidrane
c6689b3093 stm32h7 SDMMC support IDMA, Interrupt driven, pullups and SDIO
* stm32h7:Supports ARMV7M Stack check
* stm32h7:sdmmc bug fix writting address 0
* stm32h7:sdmmc Clean up timming
* stm32f7:Kconfig typos, formating
* stm32f7:sdmmc use binary not
* stm32f7:nxstyle formatting
* stm32h7:SDMMC Kconfig add Block Setup, Preflight, Delayed Invalidate
* stm32h7:Correct value of ICR reset
* stm32h7:SDMMC support IDMA, Interrupt driven, pullups and SDIO
* stm32h7:Add AXI
* stm32h7:Workaround for Errata 2.2.9 Reading from AXI SRAM may lead to data read corruption
2019-09-19 16:13:24 +00:00
David Sidrane
64fb11c1b8 Merged in david_s5/nuttx/master_h7 (pull request #1012)
Master h7

* stm32h7:spi allow more clock sources

* stm32h7 has ARCH_HAVE_I2CRESET

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-20 14:41:13 +00:00
Gregory Nutt
bcfabcbe53 This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files
Squashed commit of the following:

    arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h:  Add MCM register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h:  Add memory map definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h:  Add CMU register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h:  Add PCC register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h:  Add SCG register definition file.
    arch/arm/src/s32k1xx:  Add initial Make.defs files.
    Basic configuration logic for the S32K1 family.
2019-08-12 12:12:58 -06:00