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19143 Commits

Author SHA1 Message Date
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode 
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm" 
This reverts commit 9b7f9867aa.
 2022-05-01 11:31:01 +03:00
Xiang Xiao
a021177de8 arch: Fix the style found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:29:44 +03:00
chao.an
5db447623d arm/cxd56xx/lc823450/rp2040: replace arch testset to board implement 
This patch to resolve the regression which leads to the breakage of spresense:smp

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-01 06:38:25 +09:00
chao.an
3ec2f70046 arch/arm/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
8951b0135b arch/cortex-[a|r]/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
5677fe2153 arch/cortex-m/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
a560eb5f8d arch/arm/Make.defs: unify common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
Xiang Xiao
2a95be5086 arch/avr: Remvoe the error message when toolchain can't find 
to avoid blocking the basic ci check

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-30 01:20:11 -03:00
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Simon Filgis
385519302e Corrected typo in sam_spi.c. Debaugcall needs cs not if as ref... 
Signed-off-by: Simon Filgis <simon@ingenieurbuero-filgis.de>
 2022-04-30 03:13:38 +08:00
Oki Minabe
c38234e342 armv7-a/r: use cps instruction to change cpu mode 
Summary:
- Use CPS instruction to change cpu mode for code simplification
- CPS which changes cpu mode is available in armv6 and above

Impact:
- armv7-a/r

Testing:
- smp and ostest on sabre-6quad:smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-04-30 03:13:22 +08:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr 
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
 2022-04-29 23:13:16 +08:00
Sergey Nikitenko
19c5ac9135 stm32l4 fix ECCR comment 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3cc8d7d52a stm32l4 rtcc register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
0b9a36d142 stm32l4 fix tim channel range checking 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
541b03b787 stm32l4 TIM register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
57c64d327e stm32l4 FLASH_CR_FSTPG register fix 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
50fb3b5dc0 stm32l4 fixing proper register name RCC_APB1ENR1_PWREN 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
b73e89a674 stm32l4 RCC multi-bit field fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
7e4193c4a3 stm32l4 remove useless RTCPRE setup 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
9850766d07 stm32l4 RCC SW/SWS comment fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3da7706db8 stm32l4+ DMAMUX register fix 2022-04-29 09:30:09 +03:00
Abdelatif Guettouche
da273fce0b arch/xtensa: Replace the xcp context with stack context to improve context switching 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-29 02:51:41 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file 
Contains the code for the user process signal trampoline.
 2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function 
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
 2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv 
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
 2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL 
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
 2022-04-29 02:02:15 +08:00
Xiang Xiao
2dbf826c19 config: It's enough to let LTO_FULL depend on ARCH_TOOLCHAIN_GNU only 
since ARCH_TOOLCHAIN_CLANG automatically select ARCH_TOOLCHAIN_GNU

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-28 11:25:00 +09:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
chao.an
042640abbf arch/arm: add support for GCC LTO 
1. Enable GCC link-time optimizer
2. Enable use of a linker plugin during link-time optimization

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:54 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation 
It will just become an empty object if FPU support is not included.
 2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
98d8d2a1ff arch/xtensa: Group all the macros in one file. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
Abdelatif Guettouche
541eabb535 xtensa_int_handlers.S: Refactor the calls to ps_setup. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
chao.an
db54b0b836 arm/assert: fix build warning on clang 
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
             stack, ptr[0], ptr[1], ptr[2], ptr[3],
             ^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
   __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
                                      ~~~~~~              ^~~~~~~~~~~

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 14:18:42 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-26 11:34:28 +03:00
Abdelatif Guettouche
aaa5316235 arch/xtensa: Simply use xtensa_createstack for CPU1 idle task. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-26 01:36:54 +08:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork 
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
 2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:23:03 +03:00
Xiang Xiao
e9f5eb0823 boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:22:46 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use 
FPU registers need to be written prior to updating CSR_STATUS
 2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 07:57:29 +03:00
Abdelatif Guettouche
3942f4d133 arch/xtensa: No need to save SP in EXCSAVE_1 when linking the interrupt 
frame with the previous frame.  The SP is already saved in A12.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
f130d8c143 xtensa_user_handler.S: Fix backtrace. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00