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Author SHA1 Message Date
Xiang Xiao
a94b7b9cca arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 16:35:52 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task 
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
chao.an
0c79ad9d8d arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_* 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use 
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
 2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic 
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
 2022-04-14 16:43:34 +08:00
Xiang Xiao
701bbaac74 sched/environ: Ensure tg_envp terminated by double '\0' 
so we can compute the whole environ string length from it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 07:49:00 +03:00
zhanghongyu
4c693239c0 fix: usrsock iovec_do skip empty iov 
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
 2022-04-14 02:47:31 +08:00
zhanghongyu
f60480a5db rpmsg_usrsock: Support the wireless ioctl which contain pointer 1/2 
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
 2022-04-14 02:47:31 +08:00
anjiahao
a191d9bc3c sched/pthread_create:fix bug,delete data_sem 
if a pthread set attr is detach,and when call pthread_create,
new thread exit quikly,new thread's tcb be free,then pthread_create
use new thread's tcb will crash.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-14 01:42:16 +08:00
Abdelatif Guettouche
a5c64adbe4 arch/Kconfig: Move the DUMP_ON_EXIT option out of the Bring-up group. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit. 
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT 
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do 
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
 2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address 
MTIMECMP0 was incorrect
 2022-04-13 21:56:21 +08:00
Xiang Xiao
4b9c74514d drivers/power: Remove activity_governor.h and greedy_governor.h 
since they aren't really used anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-13 15:38:46 +03:00
zhuyanlin
5cc4f22b43 power/governor: Remove the duplicated function prototype 
since they are declared include/nuttx/power/pm.h by:
commit 5ce181e6b7
Author: zhuyanlin <zhuyanlin1@xiaomi.com>
Date:   Mon Feb 14 15:32:40 2022 +0800

    power:govorner: add govorner to per domain.

    For mult domains scene,,
    activity and greety can be used at same time.
    Let user to select domain governor.

    Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

and add static const to g_pmgovernor

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-13 15:38:46 +03:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler 
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register 
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
anjiahao
e6f77aeb9a libc/lib_strptime:change code format & add notes 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
Xiang Xiao
96ea9b71ed libc/strptime: fix warning unused-value 
warning: value computed is not used [-Wunused-value]
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
anjiahao
6d3f14d41d libc/strptime:_conv_num skip space 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
liuhaitao
366c25682c libc/time: add strptime porting support 
lib_strptime.c copies from android bionic/libc/tzcode.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-13 10:16:42 +08:00
Jukka Laitinen
dbc163f1b0 fs/vfs/fs_truncate.c: Use ioctl to truncate on non-mountpoint inode 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-04-13 09:40:18 +08:00
chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default 
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp 
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
 2022-04-12 21:33:19 +08:00
anjiahao
c843cb8a52 libc/net:use strlcpy instead of strncpy 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 21:16:11 +08:00
anjiahao
c30705f5f0 libc/lib_glob:use strlcpy instead of memcpy 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 21:15:45 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break 
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
anjiahao
49cd445114 lib_localtime:fix unsigned compare with zero 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 17:10:14 +08:00
Lingao Meng
a56199c7dd sim: bt: Add specific bluetooth HCI number id 
Add option for attached the local bluetooth device use
specific bluetooth HCI number id.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
 2022-04-12 15:15:25 +08:00
YAMAMOTO Takashi
ade753488e .github/gcc.json: Fix space/tab inconsistency 2022-04-12 13:43:06 +08:00
SPRESENSE
64e5867a8b cxd56/spresense: Add callback mechanism to notice SDCard injection 
Add a mechanism to callback to an application to notice the SDCard
status is changed (inserted or ejected).
 2022-04-12 07:55:00 +09:00
SPRESENSE
81534df8a3 boards: cxd56xx: Add board function for scd41 sensor driver 
Add board function for SCD41 CO2, temperature and humidity sensor driver.
 2022-04-12 07:55:00 +09:00
SPRESENSE
771bd8ca17 board/spresense: Add pin selection of ILI934x 
Add Kconfig choice for selecting RST and DC pins on ILI934x LCD.
 2022-04-12 07:55:00 +09:00
SPRESENSE
22d2ef0bf4 boards: cxd56xx: Make board_late_initialize a weak function 
Add a weak_function to the board_late_initialize function so that
it can be replaced by another file, such as a user application.
 2022-04-12 07:55:00 +09:00
SPRESENSE
c2e45444ff boards: cxd56xx: Fix an issue i2c tool not working 
It caused i2c tool not to work due to i2c uninitializing processing.
Since this process is not necessary in the normal case, we will
move it to the error case.
 2022-04-12 07:55:00 +09:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver 
Add critical section to scu one-shot sequencer.
 2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning 
Add necessary include header named debug.h for using ferr and
finfo.
 2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20585
 2022-04-12 07:55:00 +09:00
chao.an
a594a5d7a8 sched/init: drivers_initialize() should be late than up_initialize() 
up_initialize
|
 ->up_serialinit
   |
    ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

drivers_initialize
|
 ->syslog_console_init
   |
    ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 07:51:34 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00