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453 Commits

Author SHA1 Message Date
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver 
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 21:03:42 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver 
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 09:10:03 -05:00
Abdelatif Guettouche
96bcf7678b risc-v/esp32c3_wifi_adapter.c: Remove a config that's only used in 
Xtensa chips.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-11 10:49:52 -03:00
Virus.V
7c20199a61 riscv/bl602:replace syslog to debugging log macros 2021-06-10 08:59:16 -05:00
Xiang Xiao
c0fdddc5d7 arch: Remove all go_nx_start from chip specifc source 
since the idle stack color is done in the common code now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-10 06:50:41 -07:00
Xiang Xiao
fa0d123f87 arch: Colorize the idle thread stack in an unified way 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
 2021-06-10 06:50:41 -07:00
Chen Wen
dbf9c87a42 risc-v/esp32c3: Support ESP32-C3 RTC driver 2021-06-10 09:33:04 -03:00
Xiang Xiao
6576306bca arch: Rename xxx_getsp to up_getsp 
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-09 10:20:02 -07:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-08 13:06:08 -07:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Gustavo Henrique Nihei
0b3c2c7603 spi: Refactor SPI Slave interface prefix to sync with I2C Slave 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
27782aca19 risc-v/esp32c3: Include missing debug.h header 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
77dfb39260 risc-v/esp32c3: Uniformize references to CPU interrupt ID 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
f53306f9af risc-v/esp32c3: Ensure internal linkage of interrupt map 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
a2bcffde73 risc-v/esp32c3: Remove unused macros 2021-06-04 23:26:13 +01:00
Abdelatif Guettouche
2d55f2659e riscv/esp32c3: Add module text allocator. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
778e3ed4ad arch/risc-v/rv32im/riscv_assert.c: Provide dummy definitions of dump 
functions when ARCH_STACKDUMP is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Abdelatif Guettouche
94ded7a695 arch/riscv/rv32im/riscv_assert.c: Fix preprocessor condition. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Janne Rosberg
7b882c3588 risc-v/mpfs: fix ext irq 1-12 
Handle irq numbers 1-12 correctly
 2021-06-04 10:14:58 -05:00
Jani Paalijarvi
ebdc7a06b1 risc-v/mpfs: add MSTimer register offsets and bitmasks 2021-06-04 10:14:58 -05:00
Janne Rosberg
f7cbed0256 risc-v/mpfs: enable up_systemreset() 2021-06-04 10:14:58 -05:00
Janne Rosberg
ec11643394 risc-v/mpfs: add sysreg register defines 
This adds minimal set of sysreg defines for MPFS
 2021-06-04 10:14:58 -05:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Sara Souza
b54be4e946 risc-v/esp32-c3: Add support for HW flow control. 2021-06-01 21:37:27 -05:00
Gustavo Henrique Nihei
24c206b3f8 risc-v/esp32c3: Add DMA support for the SPI Slave controller 2021-06-01 21:37:09 -05:00
Gustavo Henrique Nihei
15a93ae974 risc-v/esp32c3: Remove Master-only settings on SPI Slave driver 2021-06-01 21:37:09 -05:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-01 06:42:02 +09:00
Gustavo Henrique Nihei
1530b0f639 risc-v/esp32c3: Fix overwriting of registered-but-disabled interrupts 2021-05-31 09:15:40 -05:00
Gustavo Henrique Nihei
da78cf78eb risc-v/esp32c3: Remove useless parameter from DMA macro 2021-05-31 09:14:14 -05:00
Gustavo Henrique Nihei
7e15d897bd risc-v/esp32c3: Add driver for SPI Slave controller 2021-05-31 12:54:15 +01:00
chenwen
1d1dd8512f esp32&esp32c3/wifi: Support specific channel and bssid scan 2021-05-31 11:09:19 +01:00
Abdelatif Guettouche
e29da149e3 arch/riscv/src/esp32c3/esp32c3_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
08aa9ce540 arch/xtensa/src/esp32/esp32_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
0f3d94e8e8 arch/risc-v/src/esp32c3/esp32c3_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Virus.V
c6317650f9 risc-v/bl602: Add RTC support 2021-05-26 20:03:19 -03:00
Gustavo Henrique Nihei
1d940b2982 risc-v/esp32c3: Constify DMA descriptor pointer to buffer 2021-05-26 14:05:27 -03:00
Gustavo Henrique Nihei
29cae80533 risc-v/esp32c3: Fix DMA TX Burst being set to input register 2021-05-26 14:05:27 -03:00
Dong Heng
73dcbac09d riscv/esp32c3: Add ESP32-C3 AES driver 2021-05-25 11:02:59 -03:00
Govind Singh
2975050c96 arch/riscv/bl602: Fix typo in i2c driver 
Signed-off-by: Govind Singh <govind.sk85@gmail.com>
 2021-05-25 01:37:28 -05:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board 
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-05-24 22:55:44 -05:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Dong Heng
76df958e34 riscv/esp32c3: Support SPI Flash encryption read/write 2021-05-23 08:37:25 -03:00
Huang Qi
f4a0b7aedd libc: Call pthread_exit in user-space by up_pthread_exit 
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.

* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Huang Qi
81a01d089b libc/pthread: Fix comment and document issue 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Gregory Nutt
bb9b58bdde libc: Move pthread_create to user space 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: I5c447d94077debc79158686935f288e4c8e51e01
 2021-05-21 22:46:52 -06:00
Jukka Laitinen
e4fd99682e rv64gc: use PRIx64 format for alert and assert 
This fixes compilation warnings caused by number formatting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Jukka Laitinen
e79a45bb93 rv64gc/riscv_assert.c: Fix compilation without CONFIG_DEBUG_ALERT 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
chenwen
9a99d813fa risc-v/esp32c3: Support ESP32-C3 auto-sleep 2021-05-19 07:00:40 -03:00
Dong Heng
f12de4f7d9 riscv/esp32c3: Add ESP32-C3 ADC driver 2021-05-18 09:20:46 -03:00
Gustavo Henrique Nihei
26a5cb2094 risc-v/esp32c3: Add support for DMA transfers on SPI driver 2021-05-17 13:21:12 +01:00
Gustavo Henrique Nihei
132ffdd28d risc-v/esp32c3: Add burst transfer support for GDMA 2021-05-17 13:21:12 +01:00
Dong Heng
4a7f998c33 riscv/esp32c3: Fix RT timer issues 
1. Enable alarm if there is timer active
2. Wake up main thread to delete timer
3. Wake up main thread when timer is timeout in ISR
 2021-05-16 13:23:43 -05:00
Dong Heng
beed26b6bf riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver 2021-05-15 08:38:37 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Dong Heng
bd8e37bb4b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing 2021-05-07 16:46:41 -03:00
Sara Souza
50daf24242 esp32/esp32-c3: Adds two helpers to extract and include a field value 2021-05-05 01:30:03 -07:00
Abdelatif Guettouche
f3a6d80c95 esp32c3/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
Sara Souza
b01ddef61b risc-v/esp32-c3: Adds freerun wrapper 2021-05-04 15:22:26 -03:00
Gustavo Henrique Nihei
7ded22fb1a risc-v/k210: Fix SMP interrupt stack size calculation 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
e0da0bf6bd arch/risc-v: Fix interrupt stack alignment 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
f8a36f10c3 arch: Uniformize optimization flag setting across architectures 2021-04-29 19:17:16 -07:00
Gustavo Henrique Nihei
abf039b744 risc-v/rv32im: Set MAXOPTIMIZATION regardless of any debug options 2021-04-29 19:17:16 -07:00
Dong Heng
fcd5648bca riscv/esp32c3: Fix SPI Flash driver internal chip data address error 
"g_rom_flashchip" is not in fixed address between all ESP32-C3's different versions.
 2021-04-28 09:58:16 -05:00
Gustavo Henrique Nihei
edeb16123b risc-v/esp32c3: Uniformize alignment for assembly instructions 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
9e7d3cff92 risc-v/esp32c3: Improve interrupt handler documentation 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
27d32f4309 risc-v/esp32c3: Reorder register restoration on interrupt handler epiloque 2021-04-28 09:55:57 -05:00
Gustavo Henrique Nihei
66a15a6f83 risc-v/esp32c3: Fix wrong references to ESP32 2021-04-28 15:41:30 +01:00
Gustavo Henrique Nihei
7caebdd50f arch/risc-v: Fix stack alignment according to calling convention 
The RISC-V Integer Calling Convention states that the stack pointer
shall always be aligned to a 128-bit boundary upon procedure entry, both
for RV32* and RV64* ISAs (exception to the RV32E ISA, which must follow a
specific convention)
 2021-04-27 23:12:20 -05:00
Gustavo Henrique Nihei
016652f7d7 risc-v/esp32c3: Change ESP32C3_RT_TIMER_TASK_PRIORITY comment into help text 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
9df2179562 risc-v/esp32c3: Uniformize Kconfig alignment and styling 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
1e45a9329b risc-v/esp32c3: Remove inconsistent usage of comment command 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
cd6c29a126 risc-v/esp32c3: Remove redundant dependency 2021-04-27 20:43:07 -06:00
Gustavo Henrique Nihei
beefd51296 risc-v/esp32c3: Add driver for General Purpose SPI Master 2021-04-26 20:50:32 -03:00
Sara Souza
5c562c1068 risc-v/esp32-c3: Reorganize the timer logic for wireless use 2021-04-22 21:38:16 -05:00
Dong Heng
fecdd27df3 esp32 & esp32c3: Update Wi-Fi BT and Wi-Fi libraries to fix some issues 2021-04-22 07:34:06 -03:00
Sara Souza
7a80cbf93f risc-v/esp32-c3: Adds oneshot timer driver. 2021-04-22 09:13:58 +01:00
Masayuki Ishikawa
1a9e7efde5 smp: Remove CONFIG_SMP_IDLETHREAD_STACKSIZE 
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
  the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code

Impact:
- All SMP configurations

Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)

Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
 2021-04-19 21:46:39 -05:00
Masayuki Ishikawa
64f46b7f7e arch: k210: Add coloration for the idle stacks 
Summary:
- This commit adds coloration for the idle stacks

Impact:
- k210 only

Testing:
- Tested with smp and nsh configs with QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-19 01:09:22 -05:00
Masayuki Ishikawa
44bc681daa arch: fe310: Add coloration for the idle stack 
Summary:
- This commit adds coloration for the idle stack
- Also, apply la pseudo-instruction instead of lui and addi

Impact:
- fe310 only

Testing:
- Tested with nsh with QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-19 01:05:40 -05:00
Xiang Xiao
2335b69120 arch: Allocate the space from the beginning in up_stack_frame 
arch: Allocate the space from the beginning in up_stack_frame

and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-16 12:41:41 +09:00
Xiang Xiao
8640d82ce0 arch: Rename g_intstackbase to g_intstacktop 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-16 12:41:41 +09:00
Dong Heng
31854ca135 riscv/esp32c3: Fix heap end address 2021-04-12 01:36:11 -05:00
Masayuki Ishikawa
7ce1033aa2 arch: k210: Fix interrupt stack corruption in SMP mode 
Summary:
- I noticed that stack corruption happens due to recent refactoring
- This commit fixes this issue

Impact:
- SMP only

Testing:
- Tested with maix-bit:smp (QMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-11 13:00:40 -05:00
Xiang Xiao
3f67c67aaf arch: Fix the stack boundary calculation and check 
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 08:39:54 -07:00
Alin Jerpelea
231b8518b7 NuttX: Ken Pettit: update licenses to Apache 
Ken Pettit has submitted the ICLA and we can migrate the licenses
 to Apache.

Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
chenwen
4ca34ac5b5 risc-v/esp32c3: Fix the issue of getting wrong Wi-Fi password 2021-04-09 03:44:29 -05:00
chenwen
a41d37cffd arch/risc-v/src/common/riscv_initialize.c: Add telnet_initialize to riscv's up_initialize 2021-04-08 23:18:32 -05:00
Matias N
ab206687bb Replace wrong inclusion of sys/errno.h (toolchain provided) with errno.h 2021-04-07 21:27:06 -05:00
Sara Souza
0926e7c578 risc-v/esp32-c3: Fixes gargabe UART issue, refactors serial driver, changes default pins of UART 1 and fixes low baud rate issue. 2021-04-06 11:44:06 -03:00
Xiang Xiao
d62ae03bf8 arch: Move setjmp/longjmp to libc/machine 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-04 16:30:37 -07:00
Alan Carvalho de Assis
bac84de45f esp32c3: Add support to RNG driver 
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-04-03 07:20:03 -05:00
hotislandn
b4b175cb7f arch:rv64:add memory clobber to inline asm for syscall. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-04-03 00:54:23 -05:00
Alin Jerpelea
5d633d7e0b arch: risc-V: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-31 08:48:51 -07:00
chenwen
91eb70b5ef risc-v/esp32c3: Support ESP32-C3 wireless ioctl cmd 2021-03-30 12:29:11 -05:00
Brennan Ashton
0a3b20e546 syslog: Drop extra carriage return from syslog calls 2021-03-28 21:24:00 -05:00
hotislandn
6aa86b469c arch:rv64:c906:add PMP, change mem map for protect build. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-03-28 09:02:48 -05:00
Alan Carvalho de Assis
76c02afc48 esp32c3-devkit: Add board support for SPIFlash 
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-26 09:19:25 +01:00
Alan Carvalho de Assis
4f8ff0765f risc-v/esp32c3: Add SPIFlash support 
Co-Authored-By: Dong Heng <dongheng@espressif.com>
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-26 09:19:25 +01:00
Dong Heng
c55085c0d8 riscv/esp32c3: Add standard C atomic function 2021-03-25 12:02:48 -03:00