sergiotarxz/nuttx
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67a56410ee
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17658 Commits

Author SHA1 Message Date
SPRESENSE
67a56410ee arch: cxd56xx: Prohibit clock change during SPI transfer 
If the system clock is changed during the SPI transfer, the SPI data can
be corrupted. So this commit prohibits the clock change during SPI transfer,
and keep the clock until the transfer is completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
db340a8941 arch: cxd56xx: Support for suppresion of clock change 
Introduce PM_CPUFREQLOCK_FLAG_HOLD into the frequency lock mechanism in
power manager, which is used to keep the current frequency without clock
change, for example, during the transfer of a periphral.
 2021-05-20 07:23:48 +02:00
SPRESENSE
9b3a80cc37 arch: cxd56xx: Fix uart getting stuck during a clock change 
UART driver is stopped and re-started during a clock change. When a UART
interrupt is generated in each process, the unexpected behavior will
occur and a console will get stuck with UART driver. This commit fixed
each process is performed atomically.
 2021-05-20 07:23:48 +02:00
jordi
ccc8c078f9 xtensa/esp32: Fix warning "is not defined" 
Detected with "-Werror" flag
 2021-05-19 20:03:03 +01:00
Anthony Merlino
e37ce7677b Try to address CI build error and a few macro fixes. 2021-05-19 10:41:18 -07:00
Anthony Merlino
b54a4c7788 Replace more ATIM_/BTIM_ macros with GTIM_ macros 2021-05-19 10:41:18 -07:00
Anthony Merlino
58c92be39c stm32 timers: Make some register operations more readable. 2021-05-19 10:41:18 -07:00
chenwen
9a99d813fa risc-v/esp32c3: Support ESP32-C3 auto-sleep 2021-05-19 07:00:40 -03:00
Chen Wen
e44ec9e48e xtensa/esp32: Fix code nxstyle issue 2021-05-19 06:45:42 -03:00
chenwen
f7db743152 xtensa/esp32: Support auto-sleep 2021-05-19 06:45:42 -03:00
chenwen
f50160f0e1 xtensa/esp32: Support tick-less OS 2021-05-19 06:45:42 -03:00
Abdelatif Guettouche
65e9ff5a48 xtensa/esp32/esp32_start.c: Remove an old and unnecessary piece of code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-19 03:05:52 -05:00
Dong Heng
f12de4f7d9 riscv/esp32c3: Add ESP32-C3 ADC driver 2021-05-18 09:20:46 -03:00
Gustavo Henrique Nihei
26a5cb2094 risc-v/esp32c3: Add support for DMA transfers on SPI driver 2021-05-17 13:21:12 +01:00
Gustavo Henrique Nihei
132ffdd28d risc-v/esp32c3: Add burst transfer support for GDMA 2021-05-17 13:21:12 +01:00
Dong Heng
4a7f998c33 riscv/esp32c3: Fix RT timer issues 
1. Enable alarm if there is timer active
2. Wake up main thread to delete timer
3. Wake up main thread when timer is timeout in ISR
 2021-05-16 13:23:43 -05:00
Anthony Merlino
fa2b9ca43b stm32/stm32f7 tickless: Fix up_timer_getmask to be correct for the width of the timer. 2021-05-16 13:04:31 -05:00
Anthony Merlino
99a9d75cdd stm32f7: Remove references to BOARD_ENABLE_USBOTG_HSULPI. Prefer Kconfig option instead. 2021-05-16 01:02:51 -07:00
Jiuzhu Dong
73cc1f8884 driver/rtc: add config CONFIG_RTC_RPMSG_SERVER to 
N/A
select rtc rpmsg role.

Change-Id: I7f9053b070593573caa5d988c6a2e13593da6bc5
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
f082893b9a driver/rtc: add config RTC_RPMSG_SERVER_NAME to 
specified the name of remote proc(rpmsg server)

Change-Id: I0086bb43727a2bbb5e68f88907b5e4608182ef9c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
ff567124d3 driver/syslog: add config SYSLOG_RPMSG_SERVER_NAME to 
N/A

specified the name of remote proc(rpmsg server)

Change-Id: Ie270d651071e87a40a80ab489597ae18db9814f0
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 09:39:57 -03:00
Dong Heng
beed26b6bf riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver 2021-05-15 08:38:37 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Juha Niskanen
abcb67a292 Remove final remaining CONFIG_DISABLE_SIGNALS and CONFIG_DISABLE_SIGNAL 2021-05-10 17:04:38 -03:00
Nathan Hartman
8af9d39667 Documentation, comments: Minor improvements and typos fixed 2021-05-09 19:12:13 -07:00
David Sidrane
17b786399c stm32:SDIO:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
3e49d49cd9 stm32h7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
c45e03b75f stm32f7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Dong Heng
bd8e37bb4b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing 2021-05-07 16:46:41 -03:00
Harri Luhtala
e5f1069654 arch/arm/src/stm32l4/hardware/stm32l4xrxx: pinmap alternative function for SPI2 2021-05-07 05:08:05 -07:00
Raman Gopalan
9044594545 at32uc3_gpioirq.c: Fix typo: contex -> context 2021-05-06 11:25:38 -03:00
Gustavo Henrique Nihei
534c058d93 spi: Adopt CPHA as the abbreviation for clock phase 2021-05-05 16:56:07 -03:00
David Sidrane
92dba32c8c stm32h7:Allow for reuse of the OTG_ID GPIO 
Currently Nuttx doesn't seem to be any real support for OTG.
    In the future when OTG is supported. This Knob can be removed
    and drivers can enable their pin sets based on CONFIG_OTG.
    (Adding CONFIG_OTG at this time would be misleading.)
 2021-05-05 12:22:11 -04:00
David Sidrane
cd603af958 stm32f7:Allow for reuse of the OTG_ID GPIO 2021-05-05 12:22:11 -04:00
David Sidrane
8624f9a444 s32k1xx:flexcan Use inttypes in printing macro 2021-05-05 06:07:50 -07:00
David Sidrane
7fb59e4f36 kinetis:flexcan Use inttypes in printing macro 2021-05-05 06:07:50 -07:00
David Sidrane
e5ceb062f9 stm32f7:Use inttypes in printing macro 
stm32f7:SDMMC Use inttypes in printing macro

stm32f7:CAN Use inttypes in printing macro

stm32f7:DMA Use inttypes in printing macro

stm32f7:serial fix compile error from UNUSED() change
 2021-05-05 06:07:50 -07:00
David Sidrane
cbe3e120d5 stm32h7:Use inttypes in printing macros 2021-05-05 06:07:50 -07:00
raiden00pl
b721ba05aa stm32_pwm.c: fix compilation warnings 2021-05-05 09:32:58 -03:00
raiden00pl
7cb7fe3f38 stm32_pwm: fixes for PULSECOUNT support 
1. generate an indefinite number of pulses when info->count = 0
2. timers that don't support pulse-count shouldn't use pulse-count logic
 2021-05-05 09:32:58 -03:00
Sara Souza
873293cc3f xtensa/esp32: Applies REG_MASK to extract a field value 2021-05-05 01:30:03 -07:00
Sara Souza
50daf24242 esp32/esp32-c3: Adds two helpers to extract and include a field value 2021-05-05 01:30:03 -07:00
Sara Souza
cce42d5f74 xtensa/esp32: Reorganize the pins initialization and adds showprogress in __start 2021-05-05 01:30:03 -07:00
Sara Souza
afd6b26232 xtensa/esp32: Replace serialout/in and fixes the fifo counter issue 2021-05-05 01:30:03 -07:00
Abdelatif Guettouche
f3a6d80c95 esp32c3/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
Abdelatif Guettouche
e24af207f8 esp32/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
raiden00pl
7b53a5fe1c stm32_adc.c: rename a struct member in struct adccmn_data_s from 'initialized' to 'refcount' 2021-05-05 01:27:56 -07:00
Sara Souza
b01ddef61b risc-v/esp32-c3: Adds freerun wrapper 2021-05-04 15:22:26 -03:00
Gustavo Henrique Nihei
7ded22fb1a risc-v/k210: Fix SMP interrupt stack size calculation 2021-04-29 19:39:17 -07:00