Gregory Nutt
6bafdb1cdc
Remove some dangling whitespace at the end of some lines.
2017-02-18 10:20:08 -06:00
Gregory Nutt
085616d651
STM32L4: Bring power management logic from Motrola MDK into NuttX
2017-02-18 10:18:42 -06:00
Gregory Nutt
6fe94b5724
Trivial cosmetic, alignement changes.
2017-02-17 17:50:56 -06:00
Gregory Nutt
e4e7528b1a
Port STM32L4 SAI driver from MDK.
2017-02-17 15:13:36 -06:00
Gregory Nutt
377fadc816
STM32L4: Add SAI register definition header file.
2017-02-17 13:52:22 -06:00
Jussi Kivilinna
dd1aa2357b
Allow board to configure HSE clock in bypass-mode. This is needed to enable HSE with Nucleo-F746ZG board.
2017-02-17 07:15:22 -06:00
Masayuki Ishikawa
add2fbfa85
LM3S Ethernet: Fix interrupt work in the last big commit.
2017-02-17 17:40:58 +09:00
Gregory Nutt
a49b349614
C library: Add swab()
2017-02-16 14:42:27 -06:00
Gregory Nutt
3b351615be
Kinetis K66: Change necessary for correct build.
2017-02-16 11:33:36 -06:00
Spahlinger, Michael
42e8b12ec3
Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus.
2017-02-16 07:42:37 -06:00
Gregory Nutt
c3bfccf293
Kinetis PWM: Purely cosmetic changes from review.
2017-02-15 17:54:55 -06:00
David Sidrane
c83af148b1
Kinetis:Add FTM3 to PWM
2017-02-15 13:42:36 -10:00
David Sidrane
a95a6c43d3
Kinetis Support RMII clock source select
...
This defined the RMII clock source select bits and allows
the selection to be made via Kconfig
2017-02-15 13:42:36 -10:00
Gregory Nutt
1474300276
LPC43: Rename HAVE_CONSOLE to HAVE_SERIAL_CONSOLE. We can, of course, always have a some console other than a serial console.
2017-02-15 07:23:18 -06:00
Alan Carvalho de Assis
058f06cc94
Fix typos introduced in previous commit
2017-02-15 07:16:15 -06:00
Gregory Nutt
077adf863e
Merge branch 'master' of bitbucket.org:nuttx/nuttx
2017-02-14 19:31:58 -06:00
Alan Carvalho de Assis
1b996f1c7c
Add usbnsh config to Bambino 200E board
2017-02-14 19:31:39 -06:00
Gregory Nutt
4043dd4aa0
LPC43 serial: Correct conditional logi that selects /dev/ttySN. Problem noted by Alan Carvalho de Assis.
2017-02-14 19:12:11 -06:00
David Sidrane
3423a4ecc2
Kinetis: Add comment the Freedom-K66F uses KSZ8081 PHY
2017-02-14 09:15:23 -10:00
David Sidrane
35fc713931
Kinetis K64 and K66 share mpu files
2017-02-14 09:15:23 -10:00
Gregory Nutt
b4695c5ee9
hostfs: Add support for fstat().
2017-02-14 09:54:08 -06:00
David Sidrane
84b206bf7e
Kinetis K66 FMC
...
Added K66 FMC register definition
2017-02-13 14:35:52 -10:00
David Sidrane
7d80db5919
Kinetis K66 Pin Mux
2017-02-13 14:35:51 -10:00
David Sidrane
e28781ebeb
Include K66 memory map
2017-02-13 14:35:51 -10:00
David Sidrane
6597e46ce7
Define Alternate addresses for IP blocks in both AIPS0 & AIPS1
...
Added ALT version of RNGA, FTM2, DAC0 as a facility to later
define secondary access via AIPS1 to these peripherals
2017-02-13 14:35:51 -10:00
David Sidrane
bd7d7edcf8
Kinetis: Updated comment in clockconfig
2017-02-13 13:24:47 -10:00
David Sidrane
3840c802d1
Kinetis SPI and I2C are 0 based
...
The K whole family line has max 4 or each. But the supported
parts have the maximums listed below:
K46 and K66 3 SPI SPI0-SPI2
K46 and K66 4 I2C I2C0-I2C3
2017-02-13 13:24:47 -10:00
David Sidrane
ddd1f8c507
Kinetis SDHC - Enable clock after selected
2017-02-13 13:24:47 -10:00
Gregory Nutt
40f8e8b41f
Fix some backward DEBUGASSERT tests in ROMFS and FAT.
2017-02-13 14:06:39 -06:00
Manohara HK
b154531838
I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S.
...
The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor. But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's. It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition)
So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.
2017-02-13 06:33:15 -06:00
David Sidrane
a907bbc5d3
Typo up_exit.c edited online with Bitbucket
2017-02-09 20:38:15 +00:00
Gregory Nutt
3329a534f7
Remove spurious blank line.
2017-02-09 13:06:42 -06:00
Gregory Nutt
c55d8f15a1
Merged in david_s5/nuttx/upstream_bkp_fix (pull request #206 )
...
STM32 & STM32F7 Fixes the bkp reference counter issue
Approved-by: Gregory Nutt
2017-02-09 19:03:04 +00:00
David Sidrane
550d259a28
STM32F7: Fixes the bkp reference counter issue
2017-02-09 08:39:51 -10:00
David Sidrane
169b3982a2
STM32: Fixes the bkp reference counter issue
2017-02-09 08:39:51 -10:00
Gregory Nutt
a292da29d0
Costmetic changes from review of last PR.
2017-02-09 08:39:31 -10:00
David Sidrane
7262a788c4
Better granualarity and erro checking of the board's MCG settings
...
Allow for complete MCG_C2 definition from the boart.h file
Moved #ifdef out of code by setting default values for
Allow for individule bit setting in MCG_C2 for
BOARD_EXTCLOCK_MCG_C2
BOARD_MCG_C2_FCFTRIM
BOARD_MCG_C2_LOCRE0
Added range and sanity checking
2017-02-09 08:39:31 -10:00
David Sidrane
0e687121e5
arch/arm/include/kinetis/kinetis_mcg.h
2017-02-09 08:39:31 -10:00
David Sidrane
b2deadd569
Support the Indexed name LOCK->LOCK0
2017-02-09 08:39:30 -10:00
David Sidrane
eee029eec1
MCG defines are based on the MCG feature configuration
...
We define the bits as a common set of names. This means that
an index may be added to a name i.e. LOCK is LOCK0 as that is
the superset name.
2017-02-09 08:39:30 -10:00
David Sidrane
ab7b72f2e8
Kinetis chip Adding K66 and inlcuding MCG versioning
...
This includes arch/arm/include/kinetis/kinetis_mcg.h
to bring in the MCG versioning and defines the KINETIS_K66
family for the added SoCs:
--------------- ------- --- ------- ------- ------ ------ ------ -----
PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
FREQ CNT FLASH FLASH
--------------- ------- --- ------- ------- ------ ------ ------ -----
MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
2017-02-09 08:39:30 -10:00
David Sidrane
9bbd98580b
Created a kinetis MCG versioning scheme pulled in by Kinetis chip.h
...
The motvations is to version the IP blocks of the Kinetis
K series family of parts.
This added versioning and configuration features for the
Kinetis MCG IP block.
It is envisioned that in the long term as a chip is added.
The author of the new chip definitions will either find
the exact configuration in an existing chip define and
add the new chip to it Or add the MCG feature configuration
#defines to the chip ifdef list in
arch/arm/include/kinetis/kinetis_mcg.h In either case the
author should mark it as "Verified to Document Number:"
taken from the reference manual.
The version KINETIS_MCG_VERSION_UKN has been applied to
most all the SoCs in the kinetis arch prior to this commit.
The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
All K64 and K66 which not have Verified MCG configurations.
2017-02-09 08:39:30 -10:00
David Sidrane
6199d1801e
Add K66 memory map
2017-02-09 08:39:30 -10:00
David Sidrane
db65734820
Add Kinetis K66 to Kinetis Kconfig
2017-02-09 08:39:30 -10:00
David Sidrane
bdd99f5aa1
Removed ws at EOL
2017-02-09 08:39:30 -10:00
Marc Rechté
d501ffc563
Kinetis SDHC driver fixes.
2017-02-09 11:28:30 -06:00
Gregory Nutt
1d290c2b37
setvbuf: Add support for disabling I/O buffering. Initially cut; untested.
2017-02-09 09:24:44 -06:00
Gregory Nutt
e6558df4ad
SIM: Add readlink and setvbuf to nuttx-names.dat
2017-02-09 08:31:00 -06:00
Alan Carvalho de Assis
afa1066b4d
LPC43: Fix missing #endif
2017-02-08 11:52:15 -06:00
Gregory Nutt
e803e2c3f4
Costmetic changes from review of last PR.
2017-02-07 17:16:56 -06:00
