1) Operational issue
TC (Transmission complete) and TDRE (TX Buffer Empty) were transposed in imxrt_serial.c. The end result was that for unoptimised code everything worked fine, but optimised code got itself into a real mess and continually fired interrupts. The patch attached fixes this. This one would have been found much more quickly if this particular board had supported SWO :-/
2) Startup issue
There are a number of chip errata that apply to the 1052 first revision (A-suffix) that don't apply to the second (B-suffix). Those got me for a while and it's important to use an EVK_B_ dev board if you're suffering stability problems with this particular chip. However, even with that resolved with either optimised or unoptimised code when there is no SNVS (Battery Backup) power and the power is switched on the CPU appears to boot but gets stuck with timer interrupts not being generated. The CPU is running and it will execute linear code. I have determined this by putting an 'imxrt_lowputc('A'+irq)' into up_doirq. For the non-running case the output looks like this;
LLLL
this implies 4 0x0b interrupts have been generated, and nothing else. If I hit keys on the keyboard I get 'e' in the flow. 0x0b is the SVC instruction and is the mechanism by which NuttX handles task switching. 'e' is 0x24, which corresponds to the LPUART1 interrupt. Other than these, the system does not respond further but is happily in the idle loop. In this circumstance if you hit SW2 on the EVKB board though the logjam 'unjams' and normal service is established, output now looks like;
LLLLPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPLPP ...etc.
Where 'P' is 0x0f (the SYSTICK interrupt)....this is what _should_ be happening so; SYSTICK starts up after SW2 has been pressed.
From this point on everything works correctly and you can reboot the CPU, put new code into it or do whatever you wish, **provided power is not cycled off**. If power is cycled off then return to the top and go through the process again.
When there is SNVS power to the CPU then power can be switched on and off as you wish, and the CPU will boot correctly. This has been determined by putting 3V onto J6.
I think we are probably doing something naughty with the way we are starting the clocks to the timers. There are certainly some restrictions on imxrt clock manipulation which we have studiously avoided. I am investigating further and have some potential patches but even if I find the root cause it should not be included in 8.2 as the change could be disruptive.
https://github.com/zephyrproject-rtos/zephyr/pull/8535/commits: "The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer."
"This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi."
This patch reverts the WFI enable for further investigation post 8.2. With this patch in place together with the previous one my system is fully stable(*), just drinking a bit more power than I'd like.
This change decouples that upper activity-based logic from the lower random walk logic and allows use of other upper state detection logic (such as a custom, application-specific state machine).
(1) unifies the iomux definitions - previously some pins had them, and some didn't. This effectively made it impossible to use the pinmuxes without editing the header file in the standard distribution tree.
(2) unifies the pin definitions so that every pin now has a suffix. This makes it *much* easier to see when a pin is in use in your code, because it will always have a definition in your board.h file.
For anyone who is already using this CPU, a couple of small changes are needed to existing code;
In respect of (1) add IOMUX decorators to your pin definitions. You will find defaults in haardware/imxrt_iomux.h. Every pin should have a IOMUX decorator and in general the defaults should be OK. So while previously in your board.h file you might have had;
You will now have;
In respect of (2) you will need to add selectors for any function that previously only had one pinning option. There aren't many of those but LPUART1 is a good example. That just means adding into your board.h something like;
net/netlink/netlink_route.c: Add Netlink socket NETLINK_ROUTE support for getting a snopshot of the Neighbor table.
net/neighbor/neighbor_snapshot.c: Add neighbor_snapshot() that will eventually be used by the Netlink sockets. Also fixed naming violation 'struct neighbor_entry' -> 'struct neighbor_entry_s'.
include/nuttx/net/neighbor.h: Expose format of the IPv6 neighbor table for use with Netlink sockets.
STM32H7:Set the BBSRAM memory range to non-cacheable.
* armv7-m:mpu add user peripheral helper
* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE
ST placed the STM32H7 BBSRAM in the SRAM default memory region
which is cacheable. This commit sets the BBSRAM memory range
to non-cacheable.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
