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68 Commits

Author SHA1 Message Date
Abdelatif Guettouche
51283bd99a arch/risc-v/syscall.h: Fix syscall function names in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-20 13:02:54 -03:00
Abdelatif Guettouche
fb0fd36a5c arch/risc-v: Internal functions should be prefixed by "riscv_" instead 
of "up_"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-20 13:02:54 -03:00
Dong Heng
458caf2732 riscv/esp32c3: Add ESP32-C3 WLAN netcard driver 2021-03-16 10:42:32 -03:00
Masayuki Ishikawa
bb255d075c arch: risc-v: Author Masayuki Ishikawa: Update license to Apache 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-03-12 16:15:44 +08:00
Gustavo Henrique Nihei
0f508c1a5f risc-v/esp32c3: Fix erroneous index for I2C IRQ 2021-03-11 19:32:03 -03:00
Xiang Xiao
c047c1412f Remove all gap8(risc-v) arch and board source code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-03-11 10:51:11 -08:00
Xiang Xiao
c54d617f2c Remove nr5m100(risc-v) arch and board source code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-03-11 10:51:11 -08:00
hotislandn
d898bc445c arch:rv64:c906:enable DP FPU support. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-03-11 10:34:47 +08:00
hotislandn
5e50938726 arch:riscv64:basic porting for C906. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-03-10 19:23:24 +08:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Abdelatif Guettouche
10822799fb esp32c3: Add GPIO IRQ support. 
The GPIO example was also extended to include testing an interrupt pin.

Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
 2021-02-21 10:29:43 -03:00
Alan Carvalho
4a42998f36 esp32-c3: Add the GPIO driver. 
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix.  It
also includes necessary board logic to run the GPIO example with 2
outputs.

Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-21 10:29:43 -03:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support 
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-18 01:21:53 -08:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Abdelatif Guettouche
0f2b774dec arch/risc-v: Remove unused and undefined file section "Public Variables" 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-27 18:40:10 -08:00
Virus.V
3e0a84182e check bl602 license 2020-12-29 01:52:09 -08:00
yangyue
d354a2f19f fix some code style 2020-12-29 01:52:09 -08:00
Virus.V
2b8e0945a9 Fix BL602 CI Build failed. 
Modify the default configuration in KConfig.
Sync latest commit from mainline.

Remove unused demo configuration

fixup bl602 nsh defconfig cause CICD failed

Rebase from mainline code
 2020-12-29 01:52:09 -08:00
Virus.V
7e84874cb1 Reconstruct bl602 readme; move up_irq_save/restore declaration to common place 2020-12-29 01:52:09 -08:00
Virus.V
ce40edbd11 Solve the problems pointed out in the comments 2020-12-29 01:52:09 -08:00
Lei Chen
58bd873729 Add Basic support for BL602(UART timer CLIC) 2020-12-29 01:52:09 -08:00
liang
b074ebec9e fix redefined CSR_INSTRET 2020-12-23 01:34:14 -06:00
Xiang Xiao
92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h 
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-20 20:27:13 -08:00
Xiang Xiao
d42c5a0bf6 arch/risc-v: Move csr.h to common place 
since CSR definition is same for 32bit and 64bit arch

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-19 08:41:33 +09:00
Xiang Xiao
fe8122ee2b arch/risc-v: Remove duplicated declaration for up_irq_save and up_irq_restore 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-19 08:29:42 +09:00
Huang Qi
4078548ae3 risc-v: Introduce basic setjmp support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2020-12-04 09:40:07 -03:00
YAMAMOTO Takashi
9ceb61d3a9 risc-v 64-bit: Fix SCN/PRI.PTR definitions 2020-11-22 05:18:29 -08:00
YAMAMOTO Takashi
cce626b545 risc-v: Add _intmax_t and _uintmax_t 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
e99321bf9d risc-v 32-bit: Fix types to match what the compiler expects 
spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT32_TYPE
    #define __INT32_TYPE__ long int
    #define __UINT32_TYPE__ long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT64_TYPE
    #define __INT64_TYPE__ long long int
    #define __UINT64_TYPE__ long long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep LP64
    #define __LP64__ 1
    #define _LP64 1
    spacetanuki%
 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
723cc14009 risc-v: Switch int64_t from long long to long 
So that it matches what the toolchain expects.

    spacetanuki% riscv64-unknown-elf-gcc --version
    riscv64-unknown-elf-gcc (SiFive GCC 8.3.0-2019.08.0) 8.3.0
    Copyright (C) 2018 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep UINT64_TYPE
    #define __UINT64_TYPE__ long unsigned int
    spacetanuki%
 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
f752b360f6 risc-v inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
Yoshinori Sugino
444a05131c arch/risc-v/include: Fix nxstyle warnings 
No functional changes
 2020-10-10 14:24:52 +01:00
zhongan
657d1c9fdc Add and fix CSR macros listed in RISC-V spec V1.10. 
Add csr operatiing macros.

Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
 2020-09-21 07:35:56 -07:00
ligd
36a0978952 arch/risc-v/src/rv32im: update & complete risc-v rv32im arch 
1. add schedulesigaction.c
2. add SYS_save_context handling
3. Skip ECALL instruction when up_swint()

Change-Id: Id52c6dd9ee1052441957b73463c00d3fd26555c5
Signed-off-by: ligd <liguiding@fishsemi.com>
 2020-06-30 09:31:21 -03:00
Xiang Xiao
4fbbd2e3bf arch: Move PRIxMAX and SCNxMAX definition to include/stdint.h 
like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
 2020-06-10 08:24:47 +02:00
Xiang Xiao
7758eb8658 arch: Define INTx_C and UINTx_C macro 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia50ea8764880fabd3d878c95328632c761be6b43
 2020-06-10 08:24:47 +02:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS 
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
 2020-05-07 12:04:16 -06:00
Ouss4
6eb6d31c32 Fix nxstyle complaints 2020-05-06 21:56:40 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Xiang Xiao
11705ffc71 Fix nxstyle issue 2020-04-14 13:02:00 -06:00
zhongan
0d3691a460 Add fpu support. 2020-04-14 13:01:47 -06:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly 
This typo had been copied and pasted into numerous irq and syscall
headers.
 2020-04-05 22:31:15 +01:00
aenrbes
d450f5ce77
Add support for Litex VexRiscV. 2020-03-21 06:01:56 +00:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-02-23 22:27:46 +01:00
Xiang Xiao
e7d9260014 arch: Customize the typedef of size_t instead of intptr_t 
To ensure size_t same as toolchain definition in the first place and rename CXX_NEWLONG to ARCH_SIZET_LONG.  The change also check whether __SIZE_TYPE__ exist before CONFIG_ARCH_SIZET_LONG so our definition can align with toolchain(gcc/clang) definition automatically.
 2020-02-18 07:15:19 -06:00
Masayuki Ishikawa
1a4ff4c4cd arch: risc-v: Add support for PROTECTED build to rv64gc 2020-02-14 09:29:51 -06:00
Xiang Xiao
76bbed07a4 Call up_irqinitialize from irq subsystem 
Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
 2020-02-08 07:39:22 -06:00
Masayuki Ishikawa
81f1133174 ELF64 support (#220) 
* include: Introduce elf64.h and elf.h

    Added elf64.h for 64bit ELF support and moved common definitions
    from elf32.h to elf.h. Also introduced Elf_xxx to be used in
    common libraries such as binfmt.

  * binfmt, include, modlib, module: Add support for ELF64

    Elf_xxx must be used instead of Elf32_xxx to support ELF64.
    To use ELF64, CONFIG_ELF_64BIT must be enabled.

  * binfmt, modlib: Add support for relocate address

  * arch: risc-v: Add include/elf.h

  * libs: machine: Add risc-v related files.

    NOTE: Currently only supports ELF64

  * boards: maix-bit: Add elf and posix_spawn configurations

  * boards: maix-bit: Add support for module configuration
 2020-02-07 17:10:23 -06:00
Xiang Xiao
80277d1630
Refine the preprocessor conditional guard style (#190) 2020-01-31 19:07:39 +01:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189) 
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
 2020-01-31 09:24:49 -06:00