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93421a988e
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2249 Commits

Author SHA1 Message Date
Gregory Nutt
93421a988e SAMA5 ADC: If DMA is enabled, then you should be able to configuration larger DMA transfers 2013-10-27 12:04:37 -06:00
Gregory Nutt
5033b9e3d6 SAMA5 ADC: Fix sample frequency scaling and sequencer setup 2013-10-27 10:29:07 -06:00
Gregory Nutt
5c5faa3119 SAMA5 ADC: Correct setup of time compare registers 2013-10-27 09:35:30 -06:00
Gregory Nutt
4bbe259082 SAM3/4 serial: Same supersitituous change as for SAMA5 2013-10-26 16:17:07 -06:00
Gregory Nutt
017d23cdb8 SAMA5 serial: Restore logic to minimize TX interrupts. Oddly, seems to improve ADC stability 2013-10-26 16:02:07 -06:00
Gregory Nutt
f090583cb2 SAMA5 TC: Debug instrumentation 2013-10-26 14:03:30 -06:00
Gregory Nutt
48ac4dcc2e SAMA5: Register definition file for camera interface 2013-10-26 08:25:58 -06:00
Gregory Nutt
6c7528f48c arch/arm/src/sama5/sam_adc.c: Remove a warning 2013-10-25 15:18:32 -06:00
Gregory Nutt
cf3845919b Add ioctl to support software triggering of ADC/DAC conversions 2013-10-25 14:19:09 -06:00
Gregory Nutt
48bcb3f141 sam_tc.c: Fix a timer initialization bug 2013-10-25 10:05:00 -06:00
Gregory Nutt
dad8aa9781 SAMA5 ADC+TC: Several updates/fixes from ongoing debug 2013-10-25 08:46:57 -06:00
Gregory Nutt
15c2d87fb9 SAMA5 ADC+TC: Early debug fixes + lots of new debug instrumentation 2013-10-24 16:50:51 -06:00
Gregory Nutt
29342298d3 SAMA5D3x-EK: Add support for app/examples/adc 2013-10-24 15:39:56 -06:00
Gregory Nutt
0e74e0fca1 SAMA5: Add ADC-side of the logic to hook in timer/counter logic needed to drive periodic ADC sampling 2013-10-24 13:56:23 -06:00
Gregory Nutt
8710cd4352 SAMA5: Hook in timer/counter logic so that it can driver periodic ADC sampling 2013-10-24 12:35:42 -06:00
Gregory Nutt
9f5b9c20fe STM32 PWM and ADC: Add some bits that should have been cleared. From Martin Lederhilger 2013-10-24 08:27:09 -06:00
Gregory Nutt
eb648c585b Add support for the STM32F207ZE chip. From Martin Lederhilger 2013-10-24 08:25:05 -06:00
Gregory Nutt
df0fc71210 Remove carriage returns from SAMA5 TC files just commited 2013-10-23 15:39:00 -06:00
Gregory Nutt
22d7fae119 SAMA5 Timer/counter library 2013-10-23 14:53:37 -06:00
Gregory Nutt
7692af99b6 STM32 F1 DAM fix from David Sidrane 2013-10-23 14:05:26 -06:00
Gregory Nutt
6a4ffaca12 SAMA5 CAN: Update readme on how to configure CAN 2013-10-23 11:32:12 -06:00
Gregory Nutt
13e074c5d4 Update Changelog 2013-10-23 09:13:28 -06:00
Gregory Nutt
856355668c SAMA5 CAN: Driver is now code complete but still untested 2013-10-22 15:47:52 -06:00
Gregory Nutt
46b0349408 SAMA5: Beginning of a CAN driver 2013-10-21 15:52:23 -06:00
Gregory Nutt
2edc58e383 SAMA5 CAN: Add register definition file 2013-10-21 12:22:27 -06:00
Gregory Nutt
f890af8e53 SAMA5 TC: Add timer/counter register definition file 2013-10-20 14:47:02 -06:00
Gregory Nutt
84973e9956 SAMA5 TRNG: /dev/random appears to be functional 2013-10-20 12:08:39 -06:00
Gregory Nutt
386daa25ca SAMA5 TRNG: Add a /dev/random driver based on the SAMA5D3 TRNG peripheral 2013-10-20 11:38:31 -06:00
Gregory Nutt
1e2c37c04f SAMA5 WDT driver is now functional 2013-10-20 09:24:30 -06:00
Gregory Nutt
fe425e18a6 SAMA5 WDT: Miss watchdog fixes 2013-10-20 08:24:05 -06:00
Gregory Nutt
7a1d5866e5 SAMA5: Initial WDT timer (untested) 2013-10-19 12:26:47 -06:00
Gregory Nutt
49b3366eff SAMA5: Hook RTC into build system; Finish RTC alarm logic; Verify correct behavior of the basic RTC functionality 2013-10-19 10:41:20 -06:00
Gregory Nutt
0a5d287e69 SAMA5: Add GPBR register definitions 2013-10-19 10:22:21 -06:00
Gregory Nutt
d1d9cf4de6 SAMA5 RTC: Beginning of an RTC driver for the SAMA5 2013-10-18 16:56:46 -06:00
Gregory Nutt
0eea9f2ebe SAMA5: Add RTC and WDT register definition header files 2013-10-18 14:47:50 -06:00
Gregory Nutt
b661ba3e2a STM32 DMA Priority: Select the correct default for F1 and other family members 2013-10-18 14:13:53 -06:00
Gregory Nutt
1b3127149c SAMA5 LCD: Move framebuffers to center of free memory region. That creates a guard band around the framebuffers that gives a little protection from any bad writes into the framebuffer 2013-10-18 10:11:20 -06:00
Gregory Nutt
5c3f7f118c Add SDIO preflight method 2013-10-18 08:15:09 -06:00
Gregory Nutt
fd468d219f Changes to stm32_dmacapable interfaces from Mike Smith 2013-10-18 08:06:23 -06:00
Gregory Nutt
0c44715f07 STM32 DMA priority corrections from Mike Smith 2013-10-18 07:37:24 -06:00
Gregory Nutt
cda1fd00c7 Typo fixes for UART7 and UART8 DMA configs. From Mike Smith 2013-10-18 07:17:55 -06:00
Gregory Nutt
2d831bc717 SAMA5 TSD: Fix to prohibit reading samples when not valid 2013-10-17 17:26:06 -06:00
Gregory Nutt
8924101566 STM32 F103C: Correct some errors in pinmapping. From David Sidrane 2013-10-16 07:26:41 -06:00
Gregory Nutt
83982f3ef9 Misc changes to README files; Update SAMA5D3x-EK NxWM configuration to use Calibration instruction messages 2013-10-14 14:53:38 -06:00
Gregory Nutt
98ffd096a0 SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported 2013-10-13 13:08:05 -06:00
Gregory Nutt
a3bb8d3d94 SAMA5 LCDC: Move framebuffer to lower memory; I suspect some corruption by interference 2013-10-13 10:42:14 -06:00
Gregory Nutt
34557b8c6b SAMA5 LCDC: Fixed backlight PWM divider. Backlight no longer flashes 2013-10-11 17:12:35 -06:00
Gregory Nutt
1d0e7aaeff SAMA5 LCDC: Wait when the LCDC is resynchronizing (SIF); Try start-up parameters from Barebox (this still don't work) 2013-10-10 18:44:08 -06:00
Gregory Nutt
57d04d3ff5 SAMA5 LCDC: Default resolution if now RGB565; Add option to select a different output resolution than the sofware resolution (needs to the 24BPP for this LCD). 2013-10-10 18:41:42 -06:00
Gregory Nutt
c79ae66fc2 SAMA5 LCDC: Move DMA descriptors out of internal SRAM and into SDRAM. I am not completely clear, but it looks like the LCDC cannot support DMA from internal SRAM 2013-10-10 12:02:41 -06:00