Commit Graph

20 Commits

Author SHA1 Message Date
Gregory Nutt
cdd8dc72a5 Xtensa ESP32: Basically a redesign of the interrupt dispatch logic. 2016-12-16 15:36:52 -06:00
Gregory Nutt
b5e979d58f ESP32: Fix a couple of bugs associated with handling of CPU interrupts. 2016-12-14 13:31:44 -06:00
Gregory Nutt
a8e3f79494 Xtensa/ESP32: Add User Exception handler 2016-10-31 12:04:52 -06:00
Gregory Nutt
a787a99071 ESP32: Add inter-cpu interrupts 2016-10-31 08:29:28 -06:00
Gregory Nutt
85ed3dae9a Update some compilation issues 2016-10-30 15:38:51 -06:00
Gregory Nutt
fdede8099b Xtensa/ESP32: Add Level1 handler, panic handler, remove EXECHOOKS. 2016-10-30 10:57:57 -06:00
Gregory Nutt
b4b26285f1 ESP32: Add tie-asm.h 2016-10-28 10:53:14 -06:00
Gregory Nutt
76788040d5 ESP32: Add esp32_config.h 2016-10-26 15:45:03 -06:00
Gregory Nutt
650757bbf0 ESP32: Add GPIO support 2016-10-26 12:11:24 -06:00
Gregory Nutt
b8462d3e04 ESP32: Need to take priority into account when allocating CPU interrupts 2016-10-25 16:27:58 -06:00
Gregory Nutt
2a59205ffa ESP32: Add CPU interrupt managmement logic; improve level interrupt decoding. 2016-10-25 12:02:53 -06:00
Gregory Nutt
1dabbd8489 Costmetic changes 2016-10-24 16:18:30 -06:00
Gregory Nutt
6bbe55602c Xtensa: Add tie.h 2016-10-23 13:25:41 -06:00
Gregory Nutt
1fcced12eb Xtensa: Timer code now compiles okay 2016-10-23 11:31:48 -06:00
Gregory Nutt
764ef72641 Xtensa: Restore XCHAL_ naming convenction 2016-10-22 09:03:43 -06:00
Gregory Nutt
1ea22b680d Xtensa: Add timer dispatch logic 2016-10-21 13:23:28 -06:00
Gregory Nutt
9e1600b7d3 Xtensa: Trivial interrupt-related changes 2016-10-20 12:56:35 -06:00
Gregory Nutt
5c3afd088e Xtensa: A little more interrupt handling logic 2016-10-20 11:44:14 -06:00
Gregory Nutt
6f35ced002 ESP32: Add peripheral interrupt IRQ numbers 2016-10-15 08:39:15 -06:00
Gregory Nutt
852330876b arch/xtensa: A little more ESP32 configuration logic 2016-10-12 14:50:28 -06:00