Gregory Nutt
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cdd8dc72a5
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Xtensa ESP32: Basically a redesign of the interrupt dispatch logic.
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2016-12-16 15:36:52 -06:00 |
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Gregory Nutt
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b5e979d58f
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ESP32: Fix a couple of bugs associated with handling of CPU interrupts.
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2016-12-14 13:31:44 -06:00 |
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Gregory Nutt
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a8e3f79494
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Xtensa/ESP32: Add User Exception handler
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2016-10-31 12:04:52 -06:00 |
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Gregory Nutt
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a787a99071
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ESP32: Add inter-cpu interrupts
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2016-10-31 08:29:28 -06:00 |
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Gregory Nutt
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85ed3dae9a
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Update some compilation issues
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2016-10-30 15:38:51 -06:00 |
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Gregory Nutt
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fdede8099b
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Xtensa/ESP32: Add Level1 handler, panic handler, remove EXECHOOKS.
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2016-10-30 10:57:57 -06:00 |
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Gregory Nutt
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b4b26285f1
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ESP32: Add tie-asm.h
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2016-10-28 10:53:14 -06:00 |
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Gregory Nutt
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76788040d5
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ESP32: Add esp32_config.h
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2016-10-26 15:45:03 -06:00 |
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Gregory Nutt
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650757bbf0
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ESP32: Add GPIO support
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2016-10-26 12:11:24 -06:00 |
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Gregory Nutt
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b8462d3e04
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ESP32: Need to take priority into account when allocating CPU interrupts
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2016-10-25 16:27:58 -06:00 |
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Gregory Nutt
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2a59205ffa
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ESP32: Add CPU interrupt managmement logic; improve level interrupt decoding.
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2016-10-25 12:02:53 -06:00 |
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Gregory Nutt
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1dabbd8489
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Costmetic changes
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2016-10-24 16:18:30 -06:00 |
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Gregory Nutt
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6bbe55602c
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Xtensa: Add tie.h
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2016-10-23 13:25:41 -06:00 |
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Gregory Nutt
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1fcced12eb
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Xtensa: Timer code now compiles okay
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2016-10-23 11:31:48 -06:00 |
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Gregory Nutt
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764ef72641
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Xtensa: Restore XCHAL_ naming convenction
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2016-10-22 09:03:43 -06:00 |
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Gregory Nutt
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1ea22b680d
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Xtensa: Add timer dispatch logic
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2016-10-21 13:23:28 -06:00 |
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Gregory Nutt
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9e1600b7d3
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Xtensa: Trivial interrupt-related changes
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2016-10-20 12:56:35 -06:00 |
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Gregory Nutt
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5c3afd088e
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Xtensa: A little more interrupt handling logic
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2016-10-20 11:44:14 -06:00 |
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Gregory Nutt
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6f35ced002
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ESP32: Add peripheral interrupt IRQ numbers
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2016-10-15 08:39:15 -06:00 |
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Gregory Nutt
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852330876b
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arch/xtensa: A little more ESP32 configuration logic
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2016-10-12 14:50:28 -06:00 |
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