Commit Graph

30 Commits

Author SHA1 Message Date
hujun5
cef8c598c7 arm64: Add support for FIQ interrupts
To compile arm64 NuttX, use the following command:
 ./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run,use the following command
 qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 16:56:24 -04:00
zhangyuan21
f47991e34d arch/arm64: select ARCH_HAVE_IRQTRIGGER for all arm64 chip
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-09-20 20:52:03 +08:00
Shanmin Zhang
e8550a02b9 arm64: support reboot / poweroff for qemu virt arm64
Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2023-09-20 00:40:44 +08:00
qinwei1
cb3e6667e3 arm64: add PSCI support for qemu platform
Summary
   Add ARM PCSI (Power State Coordination Interface) Support
for qemu. With the interface, Poweroff/PowerReset can be support

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-09-19 11:34:26 +08:00
qinwei1
c7e70b6967 arm64: GoldFish Platform support
Summary:
   Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android enhance
it with more featue
   The patch set goldfish as a chip

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-09-19 11:34:26 +08:00
Anner J. Bonilla
24e45d071e Pinephone Pro port just nsh
Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

make debug print hex again add board include

Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

remove ccache, add board memory map

remove board reset
2023-08-24 11:16:31 +08:00
qinwei1
630b5f32a2 arm64: IMX8 MEK board support
Summary

   Support for imx8qm MEK evaluate board

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
qinwei1
30354e5767 arm64: IMX8 platform (Cortex-A53) support
Summary

   Support for imx8 platform, this is a very initialize version

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
Xiang Xiao
bd30d1a4d5 arch: Move trustzone related setting to common place
to share the security setting between arm32 and arm64

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
qinwei1
37e69cdeb0 arch/arm64: enable for arm64 virt to choice CPU core
Summary
    Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
    the change do this

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 20:48:19 +08:00
qinwei1
d8e1022b6f arm64: add hostfs support
Sumary
   add hostfs support for arm64, it's a copy
from arm32.

Note:
   it's not support for opendir and readdir, command
like ls will not work.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 17:58:34 +08:00
zhangyuan21
f9cab5b9dc arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config
Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-31 05:33:23 -07:00
simbit18
2909260f91 arch/arm64/Kconfig: Fix help attribute
Replace help => ---help---
2023-05-10 22:51:11 +08:00
qinwei1
2eac660ff6 arm64: Updating ARCH_EARLY_PRINT support
Summary:
  Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
  You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-05-09 21:00:48 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
Xiang Xiao
454921eac7 arch/boards: Rename up_lowputc to [arm64|renesas]_lowputc
follow other arch coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-04 11:08:00 +02:00
qinwei1
d2d954f691 arm64: ARMv8-r(Cortex-R82) support( add FVP platform )
Summary:
   Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:

 - GICv3 interrupt controllers for ARMv8-r
 - PL011 UART controller(FVP)

Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
  board readme.txt

TODO: merge PL011 UART driver to common place

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-02 13:33:15 +08:00
qinwei1
4cb5ff3353 arm64: ARMv8-r(Cortex-R82) support(add ARCH_SET_VMPIDR_EL2 option)
Summary

   VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
  So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
  identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
  every CPU at boot EL2 stage.
  For some platform, the bootloader or hypervisor will do that at
  the EL2 stage, but not all.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
0841f4dbaa arm64: ARMv8-r(Cortex-R82) support
Summary:

  Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:

1. ARM Single Security State Support, ARMv8-R support only single
   security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
   and system register for EL3 is not accessible(gcc will failed when
   access these registers)
3. add base MPU configure for the platform.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4240723b78 arm64: add ARCH_EARLY_PRINT support
Summary:
  The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
e5564a9872 arm64: PSCI config support
Summory
   This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
  Add configure option for it.

Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
b989e4f3a6 arch:arm64: add support for nuttx arm64 Toolchain Selection
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
   the opton to be configured with menuconfig

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-01-29 14:37:16 +08:00
zouboan
753f46dffe arch/arm64: add support of systemreset 2022-12-07 21:17:39 +08:00
Lee Lup Yuen
b31054b1e3 arch/arm64: Add support for PINE64 PinePhone
This PR adds support for PINE64 PinePhone and the Allwinner A64 SoC (based on Arm Cortex-A53).

With this PR, PinePhone boots successfully to nsh (via microSD Card) and runs console apps.

-   `arch/arm64/Kconfig`: Added Allwinner A64 SoC

-   `boards/Kconfig`: Added PINE64 PinePhone

-   `arch/arm64/src/a64/Kconfig`: New Kconfig for Allwinner A64 SoC

-   `boards/arm64/a64/pinephone/Kconfig`: New Kconfig for PINE64 PinePhone

-   `src/a64/a64_boot.c`, `a64_boot.h`: Boot functions for Allwinner A64

-   `src/a64/a64_lowputc.S`: Low-level console output

-   `src/a64/a64_serial.c`, `a64_serial.h`: A64 Serial Driver

-   `src/a64/chip.h`: A64 SoC Definitions

-   `include/a64/chip.h`: A64 Memory Map, Generic Interrupt Controller

-   `include/a64/irq.h`: A64 Interrupts

-   `src/a64/Make.defs`: Source files for A64

-   `configs/nsh/defconfig`: Board Configuration for `pinephone:nsh`

-   `src/pinephone_appinit.c`: Init PinePhone

-   `src/pinephone_boardinit.c`: Init PinePhone

-   `src/pinephone_bringup.c`: Start PinePhone Drivers

-   `src/pinephone.h`: PinePhone Declarations

-   `include/board_memorymap.h`: PinePhone Memory Map

-   `scripts/dramboot.ld`: PinePhone Linker Script

-   `scripts/Make.defs`: Source files for PinePhone

-   `src/Makefile`: PinePhone Makefile

-   `platforms/arm/a64/boards/pinephone/index.rst`: Building and booting NuttX on PinePhone

-   `platforms/arm/a64/index.rst`: Overview of Allwinner A64

-   `introduction/supported_platforms.rst`: Added Allwinner A64

-   `introduction/detailed_support.rst`: Added Allwinner A64
2022-11-25 17:19:48 +08:00
Lee Lup Yuen
6aba739f05 arch/arm64: Add support for Generic Interrupt Controller Version 2
Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.

This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).

-   `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.

-   `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).

    Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.

-   `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.

-   `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.

-   `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.

-   `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.

-   `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.

-   `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
2022-11-20 21:44:12 -08:00
Hidenori Matsubayashi
28180b49d1 arm64: add Cortex-A57 and Cortex-A72 configurations
This change adds the following:
- Rename the board configuration name from qemu-a53 to qemu-v8a.
- Add the configurations for Cortex-A57 and Cortex-A72.

Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-14 09:27:35 +08:00
qinwei1
e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00