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f3f10a3b96
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17 Commits

Author SHA1 Message Date
Alin Jerpelea
f3f10a3b96 arch: mips: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-31 08:48:33 -07:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-02-23 22:27:46 +01:00
Ouss4
ac4049682f arch/mips: Fix the SW0 priority set by commit eb1adca 
It must be strictly greater than IPL to get serviced.
 2020-02-21 17:00:04 -06:00
Ouss4
0dc1dc605d arch/mips: When a CPU implements an External Interrupt Controller, 
use the IPL bits to control masking interrupts.
 2020-02-10 12:40:41 -06:00
Ouss4
47129b36bd arch/mips/*: Run nxstyle on the arch/mips directory. 2019-12-08 08:09:11 -06:00
Ouss4
bd45193a79 arch/mips: Add cache operations. Cache is initialized at startup (head.S) and the different operations are implemented in up_cache.S. 2019-11-23 09:16:41 -06:00
Gregory Nutt
b21c12bd18 Fix errors found in build testing: 
arch/mips/src:  Previous commit used CP0 register definitions that were not defined in the cp0.h header file.  Probably these were from the Microchip hacked up GCC toolchain but are not generally available.  Fix:  Add definitions to NuttX cp0.h header file.

mm/iob:  Eliminate some warnings about testing the value of an undefined pre-processor variable.
 2019-05-25 11:45:22 -06:00
Gregory Nutt
4d75901cc4 arch/mips/include/mips32/cp0.h: Fix some copy-paste errors that cause malformed comments and syntax errors when certain CP0 CONFIG1 bits are referenced. Note in Issue 123 by Anonymous. 2018-10-12 14:52:05 -06:00
Gregory Nutt
29136e51cc Clean up and review of header files for conformance to standards 2015-06-12 19:26:01 -06:00
Gregory Nutt
ae15c6963c Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
patacongo
469d018967 Add support for PIC32 MX1 and MX2 families 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4851 42af7a65-404d-4744-a932-0658087f49c3
 2012-06-19 19:09:14 +00:00
patacongo
88fde06d5b A few more AVR32 fixes 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4078 42af7a65-404d-4744-a932-0658087f49c3
 2011-11-03 01:16:48 +00:00
patacongo
44dc775b08 Fix some MIPS software interrupt enabling issues 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4067 42af7a65-404d-4744-a932-0658087f49c3
 2011-10-29 02:29:13 +00:00
patacongo
841867459d Adding support of PIC32MX5xx/6xx/7xx families 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4034 42af7a65-404d-4744-a932-0658087f49c3
 2011-10-10 16:52:14 +00:00
patacongo
0fee218399 Add PIC32 register definitions and assertion logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3623 42af7a65-404d-4744-a932-0658087f49c3
 2011-05-18 17:16:28 +00:00
patacongo
d88416d2c3 Add start function 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3621 42af7a65-404d-4744-a932-0658087f49c3
 2011-05-17 23:52:30 +00:00
patacongo
bb38ba608d Add MIPS32 interrupt controls 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3620 42af7a65-404d-4744-a932-0658087f49c3
 2011-05-17 14:59:27 +00:00