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2388373aa5
nuttx/arch/arm/include
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Minamiya_Natsuki 2388373aa5 Squashed commit of the following: 
Author: Alan Carvalho de Assis <acassis@gmail.com>

    Run all .h and .c files modified in last PR through nxstyle.

Author: Minamiya_Natsuki <yukihiratype2@gmail.com>

    Add FMC SDRAM for STM32H7x3 chip (#22)

    * Add FMC SDRAM for STM32H7x3 chip

    * Add FMC SDRAM for STM32H7x7

    * Nuttx Coding Standard requires one declaration per line

    * should be __ARCH_ARM_SRC_STM32H7_STM32_FMC_H

    * fix bad alignment

    * fix typo

    * fix typo

    * people can't live in furture

    * fix comment line length

    * fix more comment line length

    * fix aligenment

    * fix typo
2020-01-02 12:17:16 -03:00
..
a1x
am335x arch/arm/include/amm335x: Trivial, cosmetic changes after review 2019-01-08 08:15:04 -06:00
arm Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv6-m Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv7-a Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv7-m arch/arm/include/armv7-m/syscall.h: ARM EABI specifies that the stack should be aligned by 8 on function calls, inside the function is not required to be aligned by 8. Since these functions call svc, compiler doesn't know that the svc is a function, therefore it does not do any stack management. This change pushes an even number of args to the stack and maintains an 8 byte alignment. I've checked the assembly and it doesn't cause any more overhead that the hand written assembly. 2019-12-16 09:10:08 -06:00
armv7-r Squashed commit of the following: 2019-04-29 14:52:05 -06:00
c5471
cxd56xx Merged in alinjerpelea/nuttx (pull request #1061) 2019-10-24 14:26:02 +00:00
dm320
efm32 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
imx1
imx6 Fix lots of typos in C comments and Kconfig help text 2018-07-08 18:24:45 -06:00
imxrt Merged imxrt1020 into master 2019-04-30 16:08:46 -06:00
kinetis Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820) 2019-01-19 15:39:46 +00:00
kl arch/: Clean up some naming and spacing. 2018-06-20 15:38:06 -06:00
lc823450 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
lpc17xx_40xx Merged in jjlange/nuttx/lpc40xx (pull request #946) 2019-07-11 16:50:00 +00:00
lpc31xx
lpc43xx In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
lpc54xx symtab/Makefile: When system wide locale is set (i.e. en_US.UTF-8) then 'read' is ordered after 'readdir' even if separator is set to quotation mark and key set to 2. When C locale is used result is correct. 2019-08-14 11:02:30 -06:00
lpc214x
lpc2378
max326xx In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
moxart
nrf52 Merged in raiden00/nuttx_nrf52 (pull request #1098) 2019-12-19 15:40:56 +00:00
nuc1xx
s32k1xx arch/arm/src/s32k1xx: This commit brings in the LPSPI and LPI2C peripheral drivers from the i.MXRT which used the identical IP. 2019-08-21 11:18:40 -06:00
sam34 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
sama5
samd2l2 arch/arm/include/samd2l2/sam_adc.h: I was wrong... this header file does belong in the samd2l2 include directory. It contains IOCTL definitions that are needed by applications. Usage of a chip-specific header file is, however, not really a good portable design because it requires that the application know that it is running on a specific chip. But still, if we are going to do that, the include directory is where the header file belongs. My apologies for the bad judgement. 2019-12-16 03:53:05 -06:00
samd5e5 configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional. 2018-09-01 15:29:22 -06:00
samv7 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
stm32 Merged in raiden00/nuttx_pe (pull request #796) 2019-01-02 12:12:28 +00:00
stm32f0l0g0 Add support for STM32G070xx 2019-09-17 11:10:38 -06:00
stm32f7 *Merged in zhoukejun/nuttx_nucleo-f767zi (pull request #838) 2019-03-11 03:44:57 +00:00
stm32h7 Squashed commit of the following: 2020-01-02 12:17:16 -03:00
stm32l4 Fixed STM32L4_NUSART for STM32L433XX. (#9) 2019-12-31 07:47:06 -06:00
str71x
tiva arch/arm/include/tiva/tm4c_irq.h: Fix wrong IRQ vector number. 2019-11-06 20:43:51 -06:00
tms570 arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues 2018-04-18 08:58:36 -06:00
xmc4 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
.gitignore
arch.h
elf.h arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR. 2019-01-26 07:43:31 -06:00
inttypes.h
irq.h arch/arm: Add the initial cortex-a7 archtiecture support 2019-03-19 11:51:29 -06:00
limits.h
setjmp.h arch/arm/include/setjmp.h: Add prototypes for setjmp/longjmp functions. 2019-11-17 08:48:17 -06:00
spinlock.h Fix some typos 2019-09-17 10:46:23 -06:00
stdarg.h
syscall.h arch/arm: Add the initial cortex-a7 archtiecture support 2019-03-19 11:51:29 -06:00
tls.h
types.h