zhuyanlin f5d180bbdf xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO ...

For up_irq_disable, use XCHAL_EXCM_LEVEL
For up_irq_save,  use XCHAL_IRQ_LEVEL.
Then we can use svcall in enter_crritical_section.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

2022-02-25 20:43:03 +08:00

..

esp32

xtensa:esp32: setup software interrupt. (bit 29)

2022-02-24 00:06:43 +01:00

esp32s2

xtensa:esp32s2: setup software interrupt as swi interrupt

2022-02-24 00:06:43 +01:00

esp32s3

xtensa:esp32s3: setup software interrupt as swi interrupt.

2022-02-24 00:06:43 +01:00

lx6

arch: xtensa: Author Gregory Nutt: update licenses to Apache

2021-04-02 03:14:31 -05:00

lx7

xtensa: Add initial support for ESP32-S3

2022-01-27 13:46:50 -03:00

xtensa

xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO

2022-02-25 20:43:03 +08:00

.gitignore

…

arch.h

arch/xtensa: Remove FAR qualifier for Xtensa-specific files

2021-09-22 08:16:01 -03:00

elf.h

…

inttypes.h

arch: Omni Hoverboards: update licenses to Apache

2021-09-28 04:37:38 -07:00

irq.h

xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO

2022-02-25 20:43:03 +08:00

limits.h

arch: xtensa: Author Gregory Nutt: update licenses to Apache

2021-04-02 03:14:31 -05:00

loadstore.h

…

setjmp.h

xtensa: add setjmp.h include file

2021-11-17 02:23:45 -06:00

simcall.h

…

spinlock.h

arch&boards/xtensa: Fix some typos, references to STM/ARM code and

2020-08-27 05:48:55 -07:00

stdarg.h

arch:xtensa: add arch stdarg.h include file for xtensa

2021-08-09 17:58:25 -03:00

syscall.h

arch:xtensa: modify svcall to swint

2022-02-22 14:06:24 -03:00

types.h

arch: Add _wchar_t typedef like other basic types

2021-12-09 16:57:23 +09:00