2017-04-14 16:06:01 +02:00
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/****************************************************************************
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2019-05-27 16:16:24 +02:00
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* arch/arm/include/stm32f0l0g0/stm32f0_irq.h
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2017-04-14 16:06:01 +02:00
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*
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****************************************************************************/
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2020-04-05 23:00:04 +02:00
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/* This file should never be included directly but, rather, only indirectly
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2018-12-16 17:50:16 +01:00
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* through nuttx/irq.h
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*/
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2019-05-27 16:16:24 +02:00
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
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2018-12-16 17:50:16 +01:00
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2017-04-14 16:06:01 +02:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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2018-12-19 19:36:35 +01:00
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/stm32f0l0g0/chip.h>
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2017-04-14 16:06:01 +02:00
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/****************************************************************************
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2021-03-21 11:37:01 +01:00
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* Pre-processor Prototypes
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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2021-03-18 15:18:53 +01:00
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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2018-12-19 19:36:35 +01:00
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*
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2021-03-18 15:18:53 +01:00
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* Processor Exceptions (vectors 0-15). These common definitions can be
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* found in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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2018-12-19 19:36:35 +01:00
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
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#define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */
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#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
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#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: FLASH */
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#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS */
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#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */
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#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
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#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
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#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */
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#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
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#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
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#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */
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#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */
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#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
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#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
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#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
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#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
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#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */
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#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */
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#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */
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#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
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#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
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#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
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#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
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#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
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#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
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#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
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#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */
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#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
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#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
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#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
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#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
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#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
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#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
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#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
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#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
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#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
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#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
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#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
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#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
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#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
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#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 29) /* 29: USART5 */
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#define STM32_IRQ_USART6 (STM32_IRQ_EXTINT + 29) /* 29: USART6 */
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#define STM32_IRQ_USART7 (STM32_IRQ_EXTINT + 29) /* 29: USART7 */
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#define STM32_IRQ_USART8 (STM32_IRQ_EXTINT + 29) /* 29: USART8 */
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#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
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#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */
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#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */
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#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Types
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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#ifndef __ASSEMBLY__
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typedef void (*vic_vector_t)(uint32_t *regs);
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Inline functions
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Data
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Function Prototypes
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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#ifdef __cplusplus
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extern "C"
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2017-04-14 16:06:01 +02:00
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{
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#endif
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2018-12-16 17:50:16 +01:00
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#ifdef __cplusplus
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}
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2017-04-14 16:06:01 +02:00
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#endif
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2018-12-16 17:50:16 +01:00
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#endif /* __ASSEMBLY__ */
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2017-04-14 16:06:01 +02:00
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2019-05-27 16:16:24 +02:00
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */
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