2017-04-14 16:06:01 +02:00
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/****************************************************************************
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2021-03-08 22:39:04 +01:00
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* arch/arm/include/stm32f0l0g0/irq.h
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2017-04-14 16:06:01 +02:00
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*
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2021-03-20 21:14:02 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2017-04-14 16:06:01 +02:00
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*
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****************************************************************************/
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2020-04-05 23:00:04 +02:00
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/* This file should never be included directly but, rather, only indirectly
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2018-12-16 17:50:16 +01:00
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* through nuttx/irq.h
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*/
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2019-05-27 16:16:24 +02:00
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
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2018-12-16 17:50:16 +01:00
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2017-04-14 16:06:01 +02:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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2019-05-27 16:16:24 +02:00
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#include <arch/stm32f0l0g0/chip.h>
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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/* Common Processor Exceptions (vectors 0-15) */
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vectors 4-10: Reserved */
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#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
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2018-12-16 17:50:16 +01:00
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/* External interrupts (vectors >= 16) */
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
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2017-04-14 16:06:01 +02:00
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2021-03-18 15:18:53 +01:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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/* Include MCU-specific external interrupt definitions */
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2018-12-19 19:36:35 +01:00
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#if defined(CONFIG_ARCH_CHIP_STM32F0)
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2019-05-27 16:16:24 +02:00
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# include <arch/stm32f0l0g0/stm32f0_irq.h>
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2018-12-19 19:36:35 +01:00
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#elif defined(CONFIG_ARCH_CHIP_STM32L0)
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2019-05-27 16:16:24 +02:00
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# include <arch/stm32f0l0g0/stm32l0_irq.h>
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2019-05-27 13:48:57 +02:00
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#elif defined(CONFIG_ARCH_CHIP_STM32G0)
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2019-05-27 16:16:24 +02:00
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# include <arch/stm32f0l0g0/stm32g0_irq.h>
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2018-12-16 17:50:16 +01:00
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#else
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# error Unrecognized STM32 Cortex M0 family
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#endif
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2017-04-14 16:06:01 +02:00
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2018-12-16 17:50:16 +01:00
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#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINT)
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2017-04-14 16:06:01 +02:00
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Types
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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#ifndef __ASSEMBLY__
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typedef void (*vic_vector_t)(uint32_t *regs);
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2017-04-14 16:06:01 +02:00
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Inline functions
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Data
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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/****************************************************************************
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2018-12-16 17:50:16 +01:00
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* Public Function Prototypes
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2017-04-14 16:06:01 +02:00
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****************************************************************************/
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2018-12-16 17:50:16 +01:00
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#ifdef __cplusplus
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extern "C"
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2017-04-14 16:06:01 +02:00
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{
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#endif
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2018-12-16 17:50:16 +01:00
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#ifdef __cplusplus
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}
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2017-04-14 16:06:01 +02:00
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#endif
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2018-12-16 17:50:16 +01:00
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#endif /* __ASSEMBLY__ */
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2017-04-14 16:06:01 +02:00
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2019-05-27 16:16:24 +02:00
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */
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