nuttx/arch/arm/include/stm32f0l0g0/irq.h

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/****************************************************************************
* arch/arm/include/stm32f0l0g0/irq.h
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*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
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*
* http://www.apache.org/licenses/LICENSE-2.0
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*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
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*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
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/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/stm32f0l0g0/chip.h>
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/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
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/* Common Processor Exceptions (vectors 0-15) */
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#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
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/****************************************************************************
* Included Files
****************************************************************************/
/* Include MCU-specific external interrupt definitions */
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
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#if defined(CONFIG_ARCH_CHIP_STM32F0)
# include <arch/stm32f0l0g0/stm32f0_irq.h>
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
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#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include <arch/stm32f0l0g0/stm32l0_irq.h>
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
# include <arch/stm32f0l0g0/stm32g0_irq.h>
#else
# error Unrecognized STM32 Cortex M0 family
#endif
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#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINT)
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/****************************************************************************
* Public Types
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****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
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/****************************************************************************
* Inline functions
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****************************************************************************/
/****************************************************************************
* Public Data
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****************************************************************************/
/****************************************************************************
* Public Function Prototypes
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****************************************************************************/
#ifdef __cplusplus
extern "C"
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{
#endif
#ifdef __cplusplus
}
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#endif
#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */