2017-05-23 19:28:52 +02:00
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/****************************************************************************
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* drivers/can/mcp2515.c
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*
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2019-03-20 14:48:40 +01:00
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* Copyright (C) 2017, 2019 Gregory Nutt. All rights reserved.
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2017-05-23 19:28:52 +02:00
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* Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved.
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* Author: Alan Carvalho de Assis <acassis@gmail.com>
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2020-02-23 09:50:23 +01:00
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* Modified: Ben <disruptivesolutionsnl@gmail.com>
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2017-05-23 19:28:52 +02:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX, Atmel, nor the names of its contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2020-11-28 05:58:15 +01:00
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#include <inttypes.h>
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2017-05-23 19:28:52 +02:00
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#include <stdio.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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2019-04-12 19:37:08 +02:00
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#include <strings.h>
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2017-05-23 19:28:52 +02:00
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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2017-10-06 18:15:01 +02:00
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#include <nuttx/signal.h>
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2017-05-23 19:28:52 +02:00
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#include <nuttx/semaphore.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/can/can.h>
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#include <nuttx/can/mcp2515.h>
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#include "mcp2515.h"
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#if defined(CONFIG_CAN) && defined(CONFIG_CAN_MCP2515)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2019-03-20 14:48:40 +01:00
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2017-05-23 19:28:52 +02:00
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/* MCP2515 Configuration ****************************************************/
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2019-04-12 19:37:08 +02:00
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#define CAN_FRAME_MAX_DATA_LEN 8
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#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
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#define MCP2515_NUM_TX_BUFFERS 3
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2017-05-23 19:28:52 +02:00
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/* Bit timing */
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#define MCP2515_PROPSEG CONFIG_MCP2515_PROPSEG
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#define MCP2515_PHSEG1 CONFIG_MCP2515_PHASESEG1
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#define MCP2515_PHSEG2 CONFIG_MCP2515_PHASESEG2
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#define MCP2515_TSEG1 (MCP2515_PROPSEG + MCP2515_PHSEG1)
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#define MCP2515_TSEG2 MCP2515_PHSEG2
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2019-04-12 19:37:08 +02:00
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#define MCP2515_BRP ((uint8_t)(((float)(MCP2515_CANCLK_FREQUENCY) / \
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2017-05-23 19:28:52 +02:00
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((float)(MCP2515_TSEG1 + MCP2515_TSEG2 + 1) * \
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2017-10-27 14:11:37 +02:00
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(float)(2 * CONFIG_MCP2515_BITRATE))) - 1))
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2017-05-23 19:28:52 +02:00
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#define MCP2515_SJW CONFIG_MCP2515_SJW
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2017-10-27 14:11:37 +02:00
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#if MCP2515_PROPSEG < 1
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# error Invalid PROPSEG. It cannot be lower than 1
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#endif
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#if MCP2515_PROPSEG > 8
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# error Invalid PROPSEG. It cannot be greater than 8
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#endif
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#if MCP2515_PHSEG1 < 1
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# error Invalid PHSEG1. It cannot be lower than 1
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#endif
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#if MCP2515_PHSEG1 > 8
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# error Invalid PHSEG1. It cannot be greater than 1
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2017-05-23 19:28:52 +02:00
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#endif
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#if MCP2515_TSEG2 < 2
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# error Invalid TSEG2. It cannot be lower than 2
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#endif
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#if MCP2515_TSEG2 > 8
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# error Invalid TSEG2. It cannot be greater than 8
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#endif
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#if MCP2515_SJW > 4
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# error Invalid SJW. It cannot be greater than 4
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#endif
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/* MCP2515 RXB0 element size */
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/* MCP2515 RXB1 element size */
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/* MCP2515 Filters */
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2019-04-12 19:37:08 +02:00
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#ifndef CONFIG_MCP2515_NSTDFILTERS
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# define CONFIG_MCP2515_NSTDFILTERS 0
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#endif
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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#if (CONFIG_MCP2515_NSTDFILTERS > 128)
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# error Invalid MCP25150 number of Standard Filters
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#endif
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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#ifndef CONFIG_MCP2515_NEXTFILTERS
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# define CONFIG_MCP2515_NEXTFILTERS 0
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#endif
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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#if (CONFIG_MCP2515_NEXTFILTERS > 64)
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# error Invalid MCP25150 number of Extended Filters
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#endif
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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#define MCP2515_STDFILTER_BYTES \
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MCP2515_ALIGN_UP(CONFIG_MCP2515_NSTDFILTERS << 2)
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#define MCP2515_STDFILTER_WORDS (MCP2515_STDFILTER_BYTES >> 2)
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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#define MCP2515_EXTFILTER_BYTES \
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MCP2515_ALIGN_UP(CONFIG_MCP2515_NEXTFILTERS << 3)
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#define MCP2515_EXTFILTER_WORDS (MCP2515_EXTFILTER_BYTES >> 2)
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2017-05-23 19:28:52 +02:00
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/* MCP25150 TX buffer element size */
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/* MCP25150 TX FIFOs */
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/* Loopback mode */
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#undef MCP2515_LOOPBACK
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#if defined(CONFIG_MCP2515_LOOPBACK)
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# define MCP2515_LOOPBACK 1
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#endif
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/* Interrupts ***************************************************************/
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2019-03-20 14:48:40 +01:00
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2017-05-23 19:28:52 +02:00
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/* Interrupts Errors
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*
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* MCP2515_INT_MERR - Message Error Interrupt Flag bit
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* MCP2515_INT_ERR - Error Interrupt Flag bit (mult src in EFLG register)
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*/
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#define MCP2515_ERROR_INTS (MCP2515_INT_MERR | MCP2515_INT_ERR)
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/* RXn buffer interrupts
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*
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* MCP2515_INT_RX0 - Receive Buffer 0 New Message
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* MCP2515_INT_RX1 - Receive Buffer 1 New Message
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*/
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#define MCP2515_RXBUFFER_INTS (MCP2515_INT_RX0 | MCP2515_INT_RX1)
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/* TXn buffer interrupts
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*
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2020-02-23 09:50:23 +01:00
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* MCP2515_INT_TX0 - Transmit Buffer 0 Empty Interrupt
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* MCP2515_INT_TX1 - Transmit Buffer 1 Empty Interrupt
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* MCP2515_INT_TX2 - Transmit Buffer 2 Empty Interrupt
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2017-05-23 19:28:52 +02:00
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*/
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#define MCP2515_TXBUFFER_INTS (MCP2515_INT_TX0 | MCP2515_INT_TX1 | MCP2515_INT_TX2)
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2019-04-12 19:37:08 +02:00
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/* Helpers ******************************************************************/
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#define TXREGVAL(reg) priv->spi_txbuf[reg - MCP2515_TXB0CTRL]
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2017-05-23 19:28:52 +02:00
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/* Debug ********************************************************************/
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2019-03-20 14:48:40 +01:00
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2017-05-23 19:28:52 +02:00
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/* Debug configurations that may be enabled just for testing MCP2515 */
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#ifndef CONFIG_DEBUG_CAN_INFO
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# undef CONFIG_MCP2515_REGDEBUG
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#endif
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#ifdef CONFIG_MCP2515_REGDEBUG
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# define reginfo caninfo
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#else
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# define reginfo(x...)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* CAN driver state */
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enum can_state_s
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{
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MCP2515_STATE_UNINIT = 0, /* Not yet initialized */
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MCP2515_STATE_RESET, /* Initialized, reset state */
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MCP2515_STATE_SETUP, /* can_setup() has been called */
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};
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/* This structure provides the current state of a CAN peripheral */
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struct mcp2515_can_s
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{
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struct mcp2515_config_s *config; /* The constant configuration */
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2020-03-31 23:19:07 +02:00
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uint8_t state; /* See enum can_state_s */
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uint8_t nalloc; /* Number of allocated filters */
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sem_t locksem; /* Enforces mutually exclusive access */
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sem_t txfsem; /* Used to wait for TX FIFO availability */
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uint32_t btp; /* Current bit timing */
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uint8_t rxints; /* Configured RX interrupts */
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uint8_t txints; /* Configured TX interrupts */
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2017-05-23 19:28:52 +02:00
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#ifdef CONFIG_CAN_ERRORS
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2020-03-31 23:19:07 +02:00
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uint32_t olderrors; /* Used to detect the changes in error states */
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2017-05-23 19:28:52 +02:00
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#endif
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2020-03-31 23:19:07 +02:00
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uint8_t filters; /* Standard/Extende filter bit allocator. */
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uint8_t txbuffers; /* TX Buffers bit allocator. */
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2017-05-23 19:28:52 +02:00
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2019-04-12 19:37:08 +02:00
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FAR uint8_t *spi_txbuf;
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FAR uint8_t *spi_rxbuf;
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2017-05-23 19:28:52 +02:00
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#ifdef CONFIG_MCP2515_REGDEBUG
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2020-03-31 23:19:07 +02:00
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uintptr_t regaddr; /* Last register address read */
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uint32_t regval; /* Last value read from the register */
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unsigned int count; /* Number of times that the value was read */
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2017-05-23 19:28:52 +02:00
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* MCP2515 Register access */
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static void mcp2515_readregs(FAR struct mcp2515_can_s *priv, uint8_t regaddr,
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2017-05-23 20:22:49 +02:00
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FAR uint8_t *buffer, uint8_t len);
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2020-03-31 23:19:07 +02:00
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static void mcp2515_writeregs(FAR struct mcp2515_can_s *priv,
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uint8_t regaddr,
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2017-05-23 20:22:49 +02:00
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FAR const uint8_t *buffer, uint8_t len);
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2020-03-31 23:19:07 +02:00
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static void mcp2515_modifyreg(FAR struct mcp2515_can_s *priv,
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uint8_t regaddr, uint8_t mask, uint8_t value);
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2017-05-23 19:28:52 +02:00
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#ifdef CONFIG_MCP2515_REGDEBUG
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2019-03-20 14:48:40 +01:00
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static void mcp2515_dumpregs(FAR struct mcp2515_can_s *priv,
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FAR const char *msg);
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2017-05-23 19:28:52 +02:00
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#else
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# define mcp2515_dumpregs(priv,msg)
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#endif
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/* Semaphore helpers */
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2020-03-31 23:19:07 +02:00
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static int mcp2515_dev_lock(FAR struct mcp2515_can_s *priv);
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2017-10-03 23:35:24 +02:00
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#define mcp2515_dev_unlock(priv) nxsem_post(&priv->locksem)
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2017-05-23 19:28:52 +02:00
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/* MCP2515 helpers */
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#ifdef CONFIG_CAN_EXTID
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static int mcp2515_add_extfilter(FAR struct mcp2515_can_s *priv,
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FAR struct canioc_extfilter_s *extconfig);
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static int mcp2515_del_extfilter(FAR struct mcp2515_can_s *priv, int ndx);
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#endif
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static int mcp2515_add_stdfilter(FAR struct mcp2515_can_s *priv,
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FAR struct canioc_stdfilter_s *stdconfig);
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static int mcp2515_del_stdfilter(FAR struct mcp2515_can_s *priv, int ndx);
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/* CAN driver methods */
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static void mcp2515_reset(FAR struct can_dev_s *dev);
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static int mcp2515_setup(FAR struct can_dev_s *dev);
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static void mcp2515_shutdown(FAR struct can_dev_s *dev);
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static void mcp2515_rxint(FAR struct can_dev_s *dev, bool enable);
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static void mcp2515_txint(FAR struct can_dev_s *dev, bool enable);
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static int mcp2515_ioctl(FAR struct can_dev_s *dev, int cmd,
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unsigned long arg);
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static int mcp2515_remoterequest(FAR struct can_dev_s *dev, uint16_t id);
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2019-03-20 14:48:40 +01:00
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static int mcp2515_send(FAR struct can_dev_s *dev,
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FAR struct can_msg_s *msg);
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2017-05-23 19:28:52 +02:00
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static bool mcp2515_txready(FAR struct can_dev_s *dev);
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static bool mcp2515_txempty(FAR struct can_dev_s *dev);
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/* MCP2515 interrupt handling */
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#ifdef CONFIG_CAN_ERRORS
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static void mcp2515_error(FAR struct can_dev_s *dev, uint8_t status,
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uint8_t oldstatus);
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#endif
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static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset);
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2017-05-23 20:22:49 +02:00
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static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
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FAR void *arg);
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2017-05-23 19:28:52 +02:00
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/* Hardware initialization */
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static int mcp2515_hw_initialize(FAR struct mcp2515_can_s *priv);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const struct can_ops_s g_mcp2515ops =
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{
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2017-05-23 20:22:49 +02:00
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|
|
mcp2515_reset, /* co_reset */
|
|
|
|
mcp2515_setup, /* co_setup */
|
|
|
|
mcp2515_shutdown, /* co_shutdown */
|
|
|
|
mcp2515_rxint, /* co_rxint */
|
|
|
|
mcp2515_txint, /* co_txint */
|
|
|
|
mcp2515_ioctl, /* co_ioctl */
|
|
|
|
mcp2515_remoterequest, /* co_remoterequest */
|
|
|
|
mcp2515_send, /* co_send */
|
|
|
|
mcp2515_txready, /* co_txready */
|
|
|
|
mcp2515_txempty, /* co_txempty */
|
2017-05-23 19:28:52 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Private Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
static void mcp2515_read_2regs(FAR struct mcp2515_can_s *priv, uint8_t reg,
|
|
|
|
FAR uint8_t *v1, FAR uint8_t *v2)
|
|
|
|
{
|
|
|
|
priv->spi_txbuf[0] = MCP2515_READ;
|
|
|
|
priv->spi_txbuf[1] = reg;
|
|
|
|
|
|
|
|
SPI_LOCK(priv->config->spi, true);
|
|
|
|
SPI_SELECT(priv->config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
SPI_EXCHANGE(priv->config->spi, priv->spi_txbuf, priv->spi_rxbuf, 4);
|
|
|
|
SPI_SELECT(priv->config->spi, SPIDEV_CANBUS(0), false);
|
|
|
|
SPI_LOCK(priv->config->spi, false);
|
|
|
|
|
|
|
|
*v1 = priv->spi_rxbuf[2];
|
|
|
|
*v2 = priv->spi_rxbuf[3];
|
|
|
|
}
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_readregs
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Read value(s) of MCP2515 register(s).
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - A reference to the MCP2515 peripheral state
|
|
|
|
* offset - The offset to the register to read
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_readregs(FAR struct mcp2515_can_s *priv, uint8_t regaddr,
|
2017-05-23 20:22:49 +02:00
|
|
|
FAR uint8_t *buffer, uint8_t len)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config = priv->config;
|
|
|
|
#ifdef CONFIG_CANBUS_REGDEBUG
|
|
|
|
int i;
|
|
|
|
#endif
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, true);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Select the MCP2515 */
|
|
|
|
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
|
|
|
|
/* Send the READ command */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_SEND(config->spi, MCP2515_READ);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Send register to read and get the next bytes read back */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_SEND(config->spi, regaddr);
|
2017-05-23 19:28:52 +02:00
|
|
|
SPI_RECVBLOCK(config->spi, buffer, len);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Deselect the MCP2515 */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), false);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Unlock bus */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, false);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_CANBUS_REGDEBUG
|
|
|
|
for (i = 0; i < len; i++)
|
|
|
|
{
|
|
|
|
caninfo("%02x->%02x\n", regaddr, buffer[i]);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
static void mcp2515_transfer(FAR struct mcp2515_can_s *priv, uint8_t len)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config = priv->config;
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, true);
|
2019-04-12 19:37:08 +02:00
|
|
|
|
|
|
|
/* Select the MCP2515 */
|
|
|
|
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
|
|
|
|
/* Send the READ command */
|
|
|
|
|
|
|
|
SPI_EXCHANGE(config->spi, priv->spi_txbuf, priv->spi_rxbuf, len);
|
|
|
|
|
|
|
|
/* Deselect the MCP2515 */
|
|
|
|
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), false);
|
|
|
|
|
|
|
|
/* Unlock bus */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, false);
|
2019-04-12 19:37:08 +02:00
|
|
|
}
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_writeregs
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Set the value of a MCP2515 register.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - A reference to the MCP2515 peripheral state
|
|
|
|
* offset - The offset to the register to write
|
|
|
|
* regval - The value to write to the register
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
static void mcp2515_writeregs(FAR struct mcp2515_can_s *priv,
|
|
|
|
uint8_t regaddr,
|
2017-05-23 20:22:49 +02:00
|
|
|
FAR const uint8_t *buffer, uint8_t len)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config = priv->config;
|
|
|
|
#ifdef CONFIG_CANBUS_REGDEBUG
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < len; i++)
|
|
|
|
{
|
2019-03-20 14:48:40 +01:00
|
|
|
caninfo("%02x<-%02x\n", regaddr + i, buffer[i]);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, true);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Select the MCP2515 */
|
|
|
|
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
|
|
|
|
/* Send the READ command */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_SEND(config->spi, MCP2515_WRITE);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Send initial register to be written */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_SEND(config->spi, regaddr);
|
2017-05-23 19:28:52 +02:00
|
|
|
SPI_SNDBLOCK(config->spi, buffer, len);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Deselect the MCP2515 */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), false);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Unlock bus */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, false);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_modifyreg
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Modify individuals bits of MCP2515 register
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - A reference to the MCP2515 peripheral state
|
|
|
|
* offset - The offset to the register to write
|
|
|
|
* regval - The value to write to the register
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
static void mcp2515_modifyreg(FAR struct mcp2515_can_s *priv,
|
|
|
|
uint8_t regaddr, uint8_t mask, uint8_t value)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config = priv->config;
|
2019-10-28 15:02:15 +01:00
|
|
|
uint8_t wr[4] =
|
2019-04-12 19:37:08 +02:00
|
|
|
{
|
|
|
|
MCP2515_BITMOD, regaddr, mask, value
|
|
|
|
};
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, true);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Select the MCP2515 */
|
|
|
|
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
SPI_SNDBLOCK(config->spi, wr, 4);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Deselect the MCP2515 */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), false);
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Unlock bus */
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
SPI_LOCK(config->spi, false);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_dumpregs
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Dump the contents of all MCP2515 control registers
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - A reference to the MCP2515 peripheral state
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_MCP2515_REGDEBUG
|
2019-03-20 14:48:40 +01:00
|
|
|
static void mcp2515_dumpregs(FAR struct mcp2515_can_s *priv,
|
|
|
|
FAR const char *msg)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config = priv->config;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_dev_lock
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Take the semaphore that enforces mutually exclusive access to device
|
|
|
|
* structures, handling any exceptional conditions
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - A reference to the MCP2515 peripheral state
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
static int mcp2515_dev_lock(FAR struct mcp2515_can_s *priv)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
2020-03-31 23:19:07 +02:00
|
|
|
return nxsem_wait(&priv->locksem);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_add_extfilter
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Add an address filter for a extended 29 bit address.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - An instance of the MCP2515 driver state structure.
|
|
|
|
* extconfig - The configuration of the extended filter
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* A non-negative filter ID is returned on success. Otherwise a negated
|
|
|
|
* errno value is returned to indicate the nature of the error.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
static int mcp2515_add_extfilter(FAR struct mcp2515_can_s *priv,
|
2019-04-12 19:37:08 +02:00
|
|
|
FAR struct canioc_extfilter_s *extconfig)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
uint8_t regval;
|
|
|
|
uint8_t offset;
|
|
|
|
uint8_t mode = CAN_FILTER_MASK;
|
|
|
|
int ndx;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL && priv->config != NULL);
|
|
|
|
config = priv->config;
|
|
|
|
|
|
|
|
/* Get exclusive excess to the MCP2515 hardware */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Find an unused standard filter */
|
|
|
|
|
|
|
|
for (ndx = 0; ndx < config->nfilters; ndx++)
|
|
|
|
{
|
|
|
|
/* Is this filter assigned? */
|
|
|
|
|
|
|
|
if ((priv->filters & (1 << ndx)) == 0)
|
|
|
|
{
|
|
|
|
/* No, assign the filter */
|
|
|
|
|
|
|
|
DEBUGASSERT(priv->nalloc < priv->config->nfilters);
|
|
|
|
priv->filters |= (1 << ndx);
|
|
|
|
priv->nalloc++;
|
|
|
|
|
|
|
|
/* Format and write filter */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
DEBUGASSERT(extconfig->xf_id1 <= CAN_MAX_STDMSGID);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
DEBUGASSERT(extconfig->xf_id2 <= CAN_MAX_STDMSGID);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* We can reach all RXFn registers (RXFnSIDH, RXFnSIDL,
|
|
|
|
* RXFnEID8 and RXFnEID0) using this formula:
|
|
|
|
*
|
|
|
|
* filterN = RXF0reg + offset + ((priv->nalloc - 1) * 4) ;
|
|
|
|
* maskN = RXM0reg + offset
|
|
|
|
*/
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
if (priv->nalloc <= 3)
|
|
|
|
{
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
offset = 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
/* N.B. Buffer 0 is higher priority than Buffer 1
|
|
|
|
* but to separate these messages we will make this
|
|
|
|
* driver more complex. So let to consider that the
|
|
|
|
* first 2 IDs inserted in the filter will have more
|
2019-03-20 14:48:40 +01:00
|
|
|
* priority than the latest 4 IDs.
|
|
|
|
*/
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
if (extconfig->sf_prio == CAN_MSGPRIO_LOW)
|
|
|
|
{
|
|
|
|
/* Use RXB1 filters */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Use RXB0 filters */
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
switch (extconfig->xf_type)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case CAN_FILTER_DUAL:
|
|
|
|
mode = CAN_FILTER_DUAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CAN_FILTER_MASK:
|
|
|
|
mode = CAN_FILTER_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CAN_FILTER_RANGE:
|
2019-10-28 15:02:15 +01:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
/* Not supported */
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup the CONFIG Mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_CONFIG);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
if (mode == CAN_FILTER_DUAL)
|
|
|
|
{
|
|
|
|
/* The MSD IDs will be filtered by separated Mask and Filter */
|
|
|
|
|
|
|
|
/* Setup the Filter */
|
|
|
|
|
|
|
|
/* EID0 - EID7 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)(extconfig->xf_id1 & 0xff);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID0 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* EID8 - EID15 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0xff00) >> 8);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID8 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* EID16 - EID17 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0x30000) >> 16);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
/* STD0 - STD2 */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval) |
|
2020-03-31 23:19:07 +02:00
|
|
|
(uint8_t)(((extconfig->xf_id1 &
|
|
|
|
0x1c0000) >> 16) << 3);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* STD3 - STD10 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0x1fe00000) >> 21);
|
2017-05-23 19:28:52 +02:00
|
|
|
regval |= RXFSIDL_EXIDE;
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* Setup the Mask */
|
|
|
|
|
|
|
|
/* EID0 - EID7 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)(extconfig->xf_id2 & 0xff);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID0 + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* EID8 - EID15 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id2 & 0xff00) >> 8);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID8 + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* EID16 - EID17 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id2 & 0x30000) >> 16);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
/* STD0 - STD2 */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval) |
|
2020-03-31 23:19:07 +02:00
|
|
|
(uint8_t)(((extconfig->xf_id2 &
|
|
|
|
0x1c0000) >> 16) << 3);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDL + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* STD3 - STD10 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id2 & 0x1fe00000) >> 21);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDL + offset, ®val, 1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-11-28 05:56:13 +01:00
|
|
|
/* The IDs will be filtered only by the Filter register
|
|
|
|
* (Mask == Filter)
|
|
|
|
*/
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Setup the Filter */
|
|
|
|
|
|
|
|
/* EID0 - EID7 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)(extconfig->xf_id1 & 0xff);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID0 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID0 + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* EID8 - EID15 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0xff00) >> 8);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID8 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID8 + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* EID16 - EID17 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0x30000) >> 16);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* STD0 - STD2 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval) | (uint8_t)(((extconfig->xf_id1 &
|
2017-05-23 19:28:52 +02:00
|
|
|
0x1c0000) >> 16) << 3) | RXFSIDL_EXIDE;
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDL + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* STD3 - STD10 */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((extconfig->xf_id1 & 0x1fe00000) >> 21);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset, ®val, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Leave the Configuration mode, Move to Normal mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return ndx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_del_extfilter
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Remove an address filter for a standard 29 bit address.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - An instance of the MCP2515 driver state structure.
|
2019-03-20 14:48:40 +01:00
|
|
|
* ndx - The filter index previously returned by the
|
|
|
|
* mcp2515_add_extfilter().
|
2017-05-23 19:28:52 +02:00
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero (OK) is returned on success. Otherwise a negated errno value is
|
|
|
|
* returned to indicate the nature of the error.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
static int mcp2515_del_extfilter(FAR struct mcp2515_can_s *priv, int ndx)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
uint8_t regval;
|
|
|
|
uint8_t offset;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL && priv->config != NULL);
|
|
|
|
config = priv->config;
|
|
|
|
|
|
|
|
/* Check Userspace Parameters */
|
|
|
|
|
|
|
|
DEBUGASSERT(ndx >= 0 || ndx < config->nfilters);
|
|
|
|
|
|
|
|
caninfo("ndx = %d\n", ndx);
|
|
|
|
|
|
|
|
if (ndx < 0 || ndx >= config->nfilters)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get exclusive excess to the MCP2515 hardware */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Check if this filter is really assigned */
|
|
|
|
|
|
|
|
if ((priv->filters & (1 << ndx)) == 0)
|
|
|
|
{
|
|
|
|
/* No, error out */
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Release the filter */
|
|
|
|
|
|
|
|
priv->filters &= ~(1 << ndx);
|
|
|
|
|
|
|
|
DEBUGASSERT(priv->nalloc > 0);
|
|
|
|
priv->nalloc--;
|
|
|
|
|
|
|
|
/* We can reach all RXFn registers (RXFnSIDH, RXFnSIDL,
|
|
|
|
* RXFnEID8 and RXFnEID0) using this formula:
|
|
|
|
*
|
|
|
|
* filterN = RXF0reg + offset + ((priv->nalloc - 1) * 4) ;
|
|
|
|
* maskN = RXM0reg + offset
|
|
|
|
*/
|
|
|
|
|
2019-10-28 15:02:15 +01:00
|
|
|
if (ndx < 3)
|
|
|
|
{
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
offset = 4;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Setup the CONFIG Mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_CONFIG);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
/* Invalidate this filter, set its ID to 0 */
|
|
|
|
|
|
|
|
regval = 0;
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDH + offset + (ndx * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset + (ndx * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID8 + offset + (ndx * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID0 + offset + (ndx * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* Leave the Configuration mode, Move to Normal mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_add_stdfilter
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Add an address filter for a standard 11 bit address.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - An instance of the MCP2515 driver state structure.
|
|
|
|
* stdconfig - The configuration of the standard filter
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* A non-negative filter ID is returned on success. Otherwise a negated
|
|
|
|
* errno value is returned to indicate the nature of the error.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int mcp2515_add_stdfilter(FAR struct mcp2515_can_s *priv,
|
2019-04-12 19:37:08 +02:00
|
|
|
FAR struct canioc_stdfilter_s *stdconfig)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
uint8_t regval;
|
|
|
|
uint8_t offset;
|
|
|
|
uint8_t mode = CAN_FILTER_MASK;
|
|
|
|
int ndx;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL && priv->config != NULL);
|
|
|
|
config = priv->config;
|
|
|
|
|
|
|
|
/* Get exclusive excess to the MCP2515 hardware */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Find an unused standard filter */
|
|
|
|
|
|
|
|
for (ndx = 0; ndx < config->nfilters; ndx++)
|
|
|
|
{
|
|
|
|
/* Is this filter assigned? */
|
|
|
|
|
|
|
|
if ((priv->filters & (1 << ndx)) == 0)
|
|
|
|
{
|
|
|
|
/* No, assign the filter */
|
|
|
|
|
|
|
|
DEBUGASSERT(priv->nalloc < priv->config->nfilters);
|
|
|
|
priv->filters |= (1 << ndx);
|
|
|
|
priv->nalloc++;
|
|
|
|
|
|
|
|
/* Format and write filter */
|
|
|
|
|
|
|
|
DEBUGASSERT(stdconfig->sf_id1 <= CAN_MAX_STDMSGID);
|
|
|
|
|
|
|
|
DEBUGASSERT(stdconfig->sf_id2 <= CAN_MAX_STDMSGID);
|
|
|
|
|
|
|
|
/* We can reach all RXFn registers (RXFnSIDH, RXFnSIDL,
|
|
|
|
* RXFnEID8 and RXFnEID0) using this formula:
|
|
|
|
*
|
|
|
|
* filterN = RXF0reg + offset + ((priv->nalloc - 1) * 4) ;
|
|
|
|
* maskN = RXM0reg + offset
|
|
|
|
*/
|
2017-06-28 21:17:17 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
if (priv->nalloc <= 3)
|
|
|
|
{
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
offset = 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
/* N.B. Buffer 0 is higher priority than Buffer 1
|
|
|
|
* but to separate these messages we will make this
|
|
|
|
* driver more complex. So let to consider that the
|
|
|
|
* first 2 IDs inserted in the filter will have more
|
2019-03-20 14:48:40 +01:00
|
|
|
* priority than the latest 4 IDs.
|
|
|
|
*/
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
if (stdconfig->sf_prio == CAN_MSGPRIO_LOW)
|
|
|
|
{
|
|
|
|
/* Use RXB1 filters */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Use RXB0 filters */
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
switch (stdconfig->sf_type)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case CAN_FILTER_DUAL:
|
|
|
|
mode = CAN_FILTER_DUAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CAN_FILTER_MASK:
|
|
|
|
mode = CAN_FILTER_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CAN_FILTER_RANGE:
|
2019-10-28 15:02:15 +01:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
/* Not supported */
|
2019-03-20 14:48:40 +01:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup the CONFIG Mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_CONFIG);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
if (mode == CAN_FILTER_DUAL)
|
|
|
|
{
|
|
|
|
/* The MSD IDs will be filtered by separated Mask and Filter */
|
|
|
|
|
|
|
|
/* Setup the Filter */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)(((stdconfig->sf_id1) & 0x7f8) >> 3);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDH + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((stdconfig->sf_id1 & 0x07) << 5);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* Setup the Mask */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)(((stdconfig->sf_id2) & 0x7f8) >> 3);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDH + offset, ®val, 1);
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((stdconfig->sf_id2 & 0x07) << 5);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDL + offset, ®val, 1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-11-28 05:56:13 +01:00
|
|
|
/* The IDs will be filtered only by the Filter register
|
|
|
|
* (Mask == Filter)
|
|
|
|
*/
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Setup the Filter */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = (uint8_t) (((stdconfig->sf_id1) & 0x7f8) >> 3);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDH + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDH + offset, ®val, 1);
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (uint8_t)((stdconfig->sf_id1 & 0x07) << 5);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0SIDL + offset, ®val, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We need to clear the extended ID bits */
|
|
|
|
|
|
|
|
regval = 0;
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID0 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
2017-06-28 21:17:17 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0EID8 + offset +
|
2017-05-23 19:28:52 +02:00
|
|
|
((priv->nalloc - 1) * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID0 + offset, ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXM0EID8 + offset, ®val, 1);
|
|
|
|
|
|
|
|
/* Leave the Configuration mode, Move to Normal mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return ndx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_del_stdfilter
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Remove an address filter for a standard 29 bit address.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - An instance of the MCP2515 driver state structure.
|
2019-03-20 14:48:40 +01:00
|
|
|
* ndx - The filter index previously returned by the
|
|
|
|
* mcp2515_add_stdfilter().
|
2017-05-23 19:28:52 +02:00
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero (OK) is returned on success. Otherwise a negated errno value is
|
|
|
|
* returned to indicate the nature of the error.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int mcp2515_del_stdfilter(FAR struct mcp2515_can_s *priv, int ndx)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
uint8_t regval;
|
|
|
|
uint8_t offset;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL && priv->config != NULL);
|
|
|
|
config = priv->config;
|
|
|
|
|
|
|
|
/* Check Userspace Parameters */
|
|
|
|
|
|
|
|
DEBUGASSERT(ndx >= 0 || ndx < config->nfilters);
|
|
|
|
|
|
|
|
caninfo("ndx = %d\n", ndx);
|
|
|
|
|
|
|
|
if (ndx < 0 || ndx >= config->nfilters)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get exclusive excess to the MCP2515 hardware */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Check if this filter is really assigned */
|
|
|
|
|
|
|
|
if ((priv->filters & (1 << ndx)) == 0)
|
|
|
|
{
|
|
|
|
/* No, error out */
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Release the filter */
|
|
|
|
|
|
|
|
priv->filters &= ~(1 << ndx);
|
|
|
|
|
|
|
|
DEBUGASSERT(priv->nalloc > 0);
|
|
|
|
priv->nalloc--;
|
|
|
|
|
|
|
|
/* We can reach all RXFn registers (RXFnSIDH, RXFnSIDL,
|
|
|
|
* RXFnEID8 and RXFnEID0) using this formula:
|
|
|
|
*
|
|
|
|
* filterN = RXF0reg + offset + ((priv->nalloc - 1) * 4) ;
|
|
|
|
* maskN = RXM0reg + offset
|
|
|
|
*/
|
|
|
|
|
2019-10-28 15:02:15 +01:00
|
|
|
if (ndx < 3)
|
|
|
|
{
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
offset = 4;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Setup the CONFIG Mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_CONFIG);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
/* Invalidade this filter, set its ID to 0 */
|
|
|
|
|
|
|
|
regval = 0;
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDH + offset + (ndx * 4), ®val, 1);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_RXF0SIDL + offset + (ndx * 4), ®val, 1);
|
|
|
|
|
|
|
|
/* Leave the Configuration mode, Move to Normal mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_reset_lowlevel
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Reset the MCP2515 device. Called early to initialize the hardware. This
|
|
|
|
* function is called, before mcp2515_setup() and on error conditions.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_reset_lowlevel(FAR struct mcp2515_can_s *priv)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_config_s *config;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
config = priv->config;
|
|
|
|
DEBUGASSERT(config);
|
|
|
|
|
|
|
|
UNUSED(config);
|
|
|
|
|
|
|
|
/* Get exclusive access to the MCP2515 peripheral */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Send SPI reset command to MCP2515 */
|
|
|
|
|
|
|
|
SPI_LOCK(config->spi, true);
|
|
|
|
SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
|
|
|
|
SPI_SEND(config->spi, MCP2515_RESET);
|
|
|
|
SPI_LOCK(config->spi, false);
|
|
|
|
|
|
|
|
/* Wait 1ms to let MCP2515 restart */
|
|
|
|
|
2017-10-06 18:15:01 +02:00
|
|
|
nxsig_usleep(1000);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Make sure that all buffers are released.
|
|
|
|
*
|
|
|
|
* REVISIT: What if a thread is waiting for a buffer? The following
|
|
|
|
* will not wake up any waiting threads.
|
|
|
|
*/
|
|
|
|
|
2017-10-03 23:35:24 +02:00
|
|
|
nxsem_destroy(&priv->txfsem);
|
2019-04-12 19:37:08 +02:00
|
|
|
nxsem_init(&priv->txfsem, 0, MCP2515_NUM_TX_BUFFERS);
|
|
|
|
priv->txbuffers = 0b111;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Define the current state and unlock */
|
|
|
|
|
|
|
|
priv->state = MCP2515_STATE_RESET;
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_reset
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Reset the MCP2515 device. Called early to initialize the hardware. This
|
|
|
|
* function is called, before mcp2515_setup() and on error conditions.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_reset(FAR struct can_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
|
|
|
|
/* Execute the reset */
|
|
|
|
|
|
|
|
mcp2515_reset_lowlevel(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_setup
|
|
|
|
*
|
|
|
|
* Description:
|
2019-03-20 14:48:40 +01:00
|
|
|
* Configure the MCP2515. This method is called the first time that the
|
|
|
|
* MCP2515 device is opened. This will occur when the device file is
|
|
|
|
* first opened. This setup includes configuring and attaching MCP2515
|
|
|
|
* interrupts. All MCP2515 interrupts are disabled upon return.
|
2017-05-23 19:28:52 +02:00
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero on success; a negated errno on failure
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int mcp2515_setup(FAR struct can_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
config = priv->config;
|
|
|
|
DEBUGASSERT(config);
|
|
|
|
|
|
|
|
/* Get exclusive access to the MCP2515 peripheral */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* MCP2515 hardware initialization */
|
|
|
|
|
|
|
|
ret = mcp2515_hw_initialize(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
2019-03-20 14:48:40 +01:00
|
|
|
canerr("ERROR: MCP2515%d H/W initialization failed: %d\n",
|
|
|
|
config->devid, ret);
|
2017-05-23 19:28:52 +02:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Attach the MCP2515 interrupt handler. */
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
ret = config->attach(config, (mcp2515_handler_t)mcp2515_interrupt,
|
|
|
|
(FAR void *)dev);
|
2017-05-23 19:28:52 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
canerr("ERROR: Failed to attach to IRQ Handler!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable receive interrupts */
|
|
|
|
|
|
|
|
priv->state = MCP2515_STATE_SETUP;
|
|
|
|
mcp2515_rxint(dev, true);
|
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_shutdown
|
|
|
|
*
|
|
|
|
* Description:
|
2019-03-20 14:48:40 +01:00
|
|
|
* Disable the MCP2515. This method is called when the MCP2515 device is
|
|
|
|
* closed. This method reverses the operation the setup method.
|
2017-05-23 19:28:52 +02:00
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_shutdown(FAR struct can_dev_s *dev)
|
|
|
|
{
|
|
|
|
/* Nothing to do here! */
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_rxint
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable RX interrupts.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_rxint(FAR struct can_dev_s *dev, bool enable)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
config = priv->config;
|
|
|
|
DEBUGASSERT(config);
|
|
|
|
|
|
|
|
caninfo("CAN%d enable: %d\n", config->devid, enable);
|
2017-05-24 00:41:58 +02:00
|
|
|
UNUSED(config);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Enable/disable the receive interrupts */
|
|
|
|
|
|
|
|
flags = enter_critical_section();
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
{
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_modifyreg(priv, MCP2515_CANINTE,
|
|
|
|
priv->rxints | MCP2515_ERROR_INTS,
|
|
|
|
priv->rxints | MCP2515_ERROR_INTS);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_modifyreg(priv, MCP2515_CANINTE, priv->rxints, ~priv->rxints);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
leave_critical_section(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_txint
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable TX interrupts.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void mcp2515_txint(FAR struct can_dev_s *dev, bool enable)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv = dev->cd_priv;
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
DEBUGASSERT(priv && priv->config);
|
|
|
|
|
|
|
|
caninfo("CAN%d enable: %d\n", priv->config->devid, enable);
|
|
|
|
|
|
|
|
/* Enable/disable the receive interrupts */
|
|
|
|
|
|
|
|
flags = enter_critical_section();
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
{
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_modifyreg(priv, MCP2515_CANINTE,
|
|
|
|
priv->txints | MCP2515_ERROR_INTS,
|
|
|
|
priv->txints | MCP2515_ERROR_INTS);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_modifyreg(priv, MCP2515_CANINTE, priv->txints, ~priv->txints);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
leave_critical_section(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_ioctl
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* All ioctl calls will be routed through this method
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero on success; a negated errno on failure
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
static int mcp2515_ioctl(FAR struct can_dev_s *dev, int cmd,
|
|
|
|
unsigned long arg)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
int ret = -ENOTTY;
|
|
|
|
|
|
|
|
caninfo("cmd=%04x arg=%lu\n", cmd, arg);
|
|
|
|
|
|
|
|
DEBUGASSERT(dev && dev->cd_priv);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
|
|
|
|
/* Handle the command */
|
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
|
|
|
/* CANIOC_GET_BITTIMING:
|
|
|
|
* Description: Return the current bit timing settings
|
|
|
|
* Argument: A pointer to a write-able instance of struct
|
2019-03-20 14:48:40 +01:00
|
|
|
* canioc_bittiming_s in which current bit timing
|
|
|
|
* values will be returned.
|
|
|
|
* Returned Value: Zero (OK) is returned on success. Otherwise -1
|
|
|
|
* (ERROR) is returned with the errno variable set
|
|
|
|
* to indicate the nature of the error.
|
2017-05-23 19:28:52 +02:00
|
|
|
* Dependencies: None
|
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_GET_BITTIMING:
|
|
|
|
{
|
|
|
|
FAR struct canioc_bittiming_s *bt =
|
|
|
|
(FAR struct canioc_bittiming_s *)arg;
|
|
|
|
uint8_t regval;
|
|
|
|
uint8_t brp;
|
|
|
|
|
|
|
|
DEBUGASSERT(bt != NULL);
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF1, ®val, 1);
|
2019-04-12 19:37:08 +02:00
|
|
|
bt->bt_sjw = ((regval & CNF1_SJW_MASK) >> CNF1_SJW_SHIFT) + 1;
|
2019-10-28 15:02:15 +01:00
|
|
|
brp = (((regval & CNF1_BRP_MASK) >>
|
|
|
|
CNF1_BRP_SHIFT) + 1) * 2;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF2, ®val, 1);
|
2019-10-28 15:02:15 +01:00
|
|
|
bt->bt_tseg1 = ((regval & CNF2_PRSEG_MASK) >>
|
|
|
|
CNF2_PRSEG_SHIFT) + 1;
|
|
|
|
bt->bt_tseg1 += ((regval & CNF2_PHSEG1_MASK) >>
|
|
|
|
CNF2_PHSEG1_SHIFT) + 1;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF3, ®val, 1);
|
2019-10-28 15:02:15 +01:00
|
|
|
bt->bt_tseg2 = ((regval & CNF3_PHSEG2_MASK) >>
|
|
|
|
CNF3_PHSEG2_SHIFT) + 1;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
bt->bt_baud = MCP2515_CANCLK_FREQUENCY / brp /
|
|
|
|
(bt->bt_tseg1 + bt->bt_tseg2 + 1);
|
2017-05-23 19:28:52 +02:00
|
|
|
ret = OK;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* CANIOC_SET_BITTIMING:
|
|
|
|
* Description: Set new current bit timing values
|
|
|
|
* Argument: A pointer to a read-able instance of struct
|
2019-03-20 14:48:40 +01:00
|
|
|
* canioc_bittiming_s in which the new bit timing
|
|
|
|
* values are provided.
|
|
|
|
* Returned Value: Zero (OK) is returned on success. Otherwise -1
|
|
|
|
* (ERROR) is returned with the errno variable set to
|
|
|
|
* indicate the nature of the error.
|
2017-05-23 19:28:52 +02:00
|
|
|
* Dependencies: None
|
|
|
|
*
|
|
|
|
* REVISIT: There is probably a limitation here: If there are multiple
|
2019-03-20 14:48:40 +01:00
|
|
|
* threads trying to send CAN packets, when one of these threads
|
|
|
|
* reconfigures the bitrate, the MCP2515 hardware will be reset and
|
|
|
|
* the context of operation will be lost. Hence, this IOCTL can only
|
|
|
|
* safely be executed in quiescent time periods.
|
2017-05-23 19:28:52 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_SET_BITTIMING:
|
|
|
|
{
|
|
|
|
FAR const struct canioc_bittiming_s *bt =
|
|
|
|
(FAR const struct canioc_bittiming_s *)arg;
|
|
|
|
irqstate_t flags;
|
|
|
|
uint8_t brp;
|
|
|
|
uint8_t sjw;
|
|
|
|
uint8_t tseg1;
|
|
|
|
uint8_t tseg2;
|
|
|
|
uint8_t prseg;
|
|
|
|
uint8_t phseg1;
|
|
|
|
uint8_t regval;
|
|
|
|
|
|
|
|
DEBUGASSERT(bt != NULL);
|
|
|
|
DEBUGASSERT(bt->bt_baud < MCP2515_CANCLK_FREQUENCY);
|
|
|
|
DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4);
|
|
|
|
DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 16);
|
|
|
|
DEBUGASSERT(bt->bt_tseg2 > 1 && bt->bt_tseg2 <= 8);
|
|
|
|
DEBUGASSERT(bt->bt_tseg1 > bt->bt_tseg2);
|
|
|
|
DEBUGASSERT(bt->bt_tseg2 > bt->bt_sjw);
|
|
|
|
|
|
|
|
/* Extract bit timing data */
|
|
|
|
|
|
|
|
tseg1 = bt->bt_tseg1 - 1;
|
|
|
|
tseg2 = bt->bt_tseg2 - 1;
|
|
|
|
sjw = bt->bt_sjw - 1;
|
|
|
|
|
|
|
|
/* PRSEG = TSEG1 - PHSEG1
|
|
|
|
* Because we don't have PHSEG1 then let us to assume:
|
|
|
|
* PHSEG1 == PHSEG2 (PHSEG2 = TSEG2)
|
|
|
|
*
|
|
|
|
* See more at:
|
2021-04-04 11:58:11 +02:00
|
|
|
* http://www.analog.com/en/analog-dialogue/articles/
|
|
|
|
* configure-can-bit-timing.html
|
2017-06-28 21:17:17 +02:00
|
|
|
*
|
2017-05-23 19:28:52 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
phseg1 = tseg2;
|
|
|
|
prseg = tseg1 - phseg1;
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
brp = (uint32_t)(((float) MCP2515_CANCLK_FREQUENCY /
|
2017-10-27 14:15:54 +02:00
|
|
|
((float)(tseg1 + tseg2 + 1) * (float)(2 * bt->bt_baud))) - 1);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Save the value of the new bit timing register */
|
|
|
|
|
|
|
|
flags = enter_critical_section();
|
|
|
|
|
|
|
|
/* Setup the CONFIG Mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_CONFIG);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
/* Setup CNF1 register */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF1, ®val, 1);
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval & ~CNF1_BRP_MASK) |
|
|
|
|
(brp << CNF1_BRP_SHIFT);
|
|
|
|
regval = (regval & ~CNF1_SJW_MASK) |
|
|
|
|
((sjw) << CNF1_SJW_SHIFT);
|
2017-05-23 19:28:52 +02:00
|
|
|
mcp2515_writeregs(priv, MCP2515_CNF1, ®val, 1);
|
|
|
|
|
|
|
|
/* Setup CNF2 register */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF2, ®val, 1);
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval & ~CNF2_PRSEG_MASK) |
|
|
|
|
((prseg - 1) << CNF2_PRSEG_SHIFT);
|
|
|
|
regval = (regval & ~CNF2_PHSEG1_MASK) |
|
|
|
|
(phseg1 << CNF2_PHSEG1_SHIFT);
|
2017-05-23 19:28:52 +02:00
|
|
|
regval = (regval | CNF2_SAM | CNF2_BTLMODE);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CNF2, ®val, 1);
|
|
|
|
|
|
|
|
/* Setup CNF3 register */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CNF3, ®val, 1);
|
2019-03-20 14:48:40 +01:00
|
|
|
regval = (regval & ~CNF3_PHSEG2_MASK) |
|
|
|
|
(tseg2 << CNF3_PHSEG2_SHIFT);
|
2017-05-23 19:28:52 +02:00
|
|
|
regval = (regval | CNF3_SOF);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CNF3, ®val, 1);
|
|
|
|
|
|
|
|
/* Leave the Configuration mode, Move to Normal mode */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
|
|
|
|
mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
|
|
|
|
|
|
|
|
leave_critical_section(flags);
|
|
|
|
|
|
|
|
ret = OK;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
/* CANIOC_ADD_EXTFILTER:
|
|
|
|
* Description: Add an address filter for a extended 29 bit
|
|
|
|
* address.
|
|
|
|
* Argument: A reference to struct canioc_extfilter_s
|
|
|
|
* Returned Value: A non-negative filter ID is returned on success.
|
|
|
|
* Otherwise -1 (ERROR) is returned with the errno
|
|
|
|
* variable set to indicate the nature of the error.
|
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_ADD_EXTFILTER:
|
|
|
|
{
|
|
|
|
DEBUGASSERT(arg != 0);
|
2019-03-20 14:48:40 +01:00
|
|
|
ret = mcp2515_add_extfilter(priv,
|
|
|
|
(FAR struct canioc_extfilter_s *)arg);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* CANIOC_DEL_EXTFILTER:
|
2019-03-20 14:48:40 +01:00
|
|
|
* Description: Remove an address filter for a standard 29 bit
|
|
|
|
* address.
|
2017-05-23 19:28:52 +02:00
|
|
|
* Argument: The filter index previously returned by the
|
|
|
|
* CANIOC_ADD_EXTFILTER command
|
2019-03-20 14:48:40 +01:00
|
|
|
* Returned Value: Zero (OK) is returned on success. Otherwise -1
|
|
|
|
* (ERROR) is returned with the errno variable set to
|
|
|
|
* indicate the nature of the error.
|
2017-05-23 19:28:52 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_DEL_EXTFILTER:
|
|
|
|
{
|
|
|
|
FAR int *ndx = (FAR int *)((uintptr_t)arg);
|
|
|
|
|
|
|
|
DEBUGASSERT(*ndx <= priv->config->nfilters);
|
|
|
|
ret = mcp2515_del_extfilter(priv, (int)*ndx);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* CANIOC_ADD_STDFILTER:
|
|
|
|
* Description: Add an address filter for a standard 11 bit
|
|
|
|
* address.
|
|
|
|
* Argument: A reference to struct canioc_stdfilter_s
|
|
|
|
* Returned Value: A non-negative filter ID is returned on success.
|
|
|
|
* Otherwise -1 (ERROR) is returned with the errno
|
|
|
|
* variable set to indicate the nature of the error.
|
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_ADD_STDFILTER:
|
|
|
|
{
|
|
|
|
DEBUGASSERT(arg != 0);
|
2019-03-20 14:48:40 +01:00
|
|
|
ret = mcp2515_add_stdfilter(priv,
|
|
|
|
(FAR struct canioc_stdfilter_s *)arg);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* CANIOC_DEL_STDFILTER:
|
2019-03-20 14:48:40 +01:00
|
|
|
* Description: Remove an address filter for a standard 11 bit
|
|
|
|
* address.
|
2017-05-23 19:28:52 +02:00
|
|
|
* Argument: The filter index previously returned by the
|
|
|
|
* CANIOC_ADD_STDFILTER command
|
2019-03-20 14:48:40 +01:00
|
|
|
* Returned Value: Zero (OK) is returned on success. Otherwise -1
|
|
|
|
* (ERROR) is returned with the errno variable set to
|
|
|
|
* indicate the nature of the error.
|
2017-05-23 19:28:52 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
case CANIOC_DEL_STDFILTER:
|
|
|
|
{
|
|
|
|
FAR int *ndx = (FAR int *)((uintptr_t)arg);
|
|
|
|
|
|
|
|
DEBUGASSERT(*ndx <= priv->config->nfilters);
|
|
|
|
ret = mcp2515_del_stdfilter(priv, (int)*ndx);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Unsupported/unrecognized command */
|
|
|
|
|
|
|
|
default:
|
|
|
|
canerr("ERROR: Unrecognized command: %04x\n", cmd);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_remoterequest
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Send a remote request
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero on success; a negated errno on failure
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int mcp2515_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
|
|
|
|
{
|
|
|
|
/* REVISIT: Remote request not implemented */
|
|
|
|
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_send
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Send one can message.
|
|
|
|
*
|
|
|
|
* One CAN-message consists of a maximum of 10 bytes. A message is
|
|
|
|
* composed of at least the first 2 bytes (when there are no data bytes).
|
|
|
|
*
|
|
|
|
* Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier
|
|
|
|
* Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier
|
|
|
|
* Bit 4: Remote Transmission Request (RTR)
|
|
|
|
* Bits 0-3: Data Length Code (DLC)
|
|
|
|
* Bytes 2-10: CAN data
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero on success; a negated errno on failure
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
FAR struct mcp2515_config_s *config;
|
|
|
|
uint8_t regval;
|
2019-04-12 19:37:08 +02:00
|
|
|
uint8_t txbuf;
|
2017-05-23 19:28:52 +02:00
|
|
|
unsigned int nbytes;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv && priv->config);
|
|
|
|
config = priv->config;
|
|
|
|
|
|
|
|
caninfo("CAN%d\n", config->devid);
|
2020-11-28 05:58:15 +01:00
|
|
|
caninfo("CAN%d ID: %" PRId32 " DLC: %d\n",
|
|
|
|
config->devid, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
|
2017-05-24 00:41:58 +02:00
|
|
|
UNUSED(config);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
/* Get exclusive access to the MCP2515 peripheral */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = mcp2515_dev_lock(priv);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
/* Acquire buffer */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = nxsem_wait(&priv->txfsem);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
DEBUGASSERT(priv->txbuffers != 0);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
txbuf = ffs(priv->txbuffers) - 1;
|
|
|
|
priv->txbuffers &= ~(1 << txbuf);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
/* Select one empty transmit buffer */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Setup the MCP2515 TX Buffer with the message to send */
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
if (msg->cm_hdr.ch_extid)
|
|
|
|
{
|
|
|
|
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID);
|
|
|
|
|
|
|
|
/* EID7 - EID0 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0xff);
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0EID0) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* EID15 - EID8 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0xff00) >> 8;
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0EID8) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* EID17 and EID16 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0x30000) >> 16;
|
|
|
|
regval |= TXBSIDL_EXIDE;
|
|
|
|
|
|
|
|
/* STD2 - STD0 */
|
|
|
|
|
2021-03-28 21:52:56 +02:00
|
|
|
regval |= (msg->cm_hdr.ch_id & 0x1c0000) >> 13;
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0SIDL) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* STD10 - STD3 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0x1fe00000) >> 21;
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0SIDH) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID);
|
|
|
|
|
|
|
|
/* Setup the Standard ID of the message to send */
|
|
|
|
|
|
|
|
/* STD10 - STD3 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0x7f8) >> 3;
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0SIDH) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* STD2 - STD0 */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_id & 0x007) << 5;
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0SIDL) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup the DLC */
|
|
|
|
|
|
|
|
regval = (msg->cm_hdr.ch_dlc & 0xf);
|
|
|
|
|
|
|
|
if (msg->cm_hdr.ch_rtr)
|
|
|
|
{
|
|
|
|
regval |= TXBDLC_RTR;
|
|
|
|
}
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0DLC) = regval;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Fill the data buffer */
|
|
|
|
|
|
|
|
nbytes = msg->cm_hdr.ch_dlc;
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
memcpy(&TXREGVAL(MCP2515_TXB0D0), msg->cm_data, nbytes);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
TXREGVAL(MCP2515_TXB0CTRL) = MCP2515_LOAD_TXB(txbuf);
|
|
|
|
|
|
|
|
mcp2515_transfer(priv, SPI_TRANSFER_BUF_LEN);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
/* Request to send */
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
priv->spi_txbuf[0] = MCP2515_RTS(txbuf);
|
|
|
|
mcp2515_transfer(priv, 1);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
mcp2515_dev_unlock(priv);
|
|
|
|
|
|
|
|
/* Report that the TX transfer is complete to the upper half logic. Of
|
|
|
|
* course, the transfer is not complete, but this early notification
|
|
|
|
* allows the upper half logic to free resources sooner.
|
|
|
|
*
|
|
|
|
* REVISIT: Should we disable interrupts? can_txdone() was designed to
|
|
|
|
* be called from an interrupt handler and, hence, may be unsafe when
|
|
|
|
* called from the tasking level.
|
|
|
|
*/
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
can_txdone(dev);
|
2017-05-23 19:28:52 +02:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_txready
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the MCP2515 hardware can accept another TX message.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* True if the MCP2515 hardware is ready to accept another TX message.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static bool mcp2515_txready(FAR struct can_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
return priv->txbuffers != 0;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_txempty
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if all message have been sent. If for example, the MCP2515
|
|
|
|
* hardware implements FIFOs, then this would mean the transmit FIFO is
|
|
|
|
* empty. This method is called when the driver needs to make sure that
|
|
|
|
* all characters are "drained" from the TX hardware before calling
|
|
|
|
* co_shutdown().
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - An instance of the "upper half" can driver state structure.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* True if there are no pending TX transfers in the MCP2515 hardware.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static bool mcp2515_txempty(FAR struct can_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
return priv->txbuffers == (1 << MCP2515_NUM_TX_BUFFERS) - 1;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_error
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Report a CAN error
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - CAN-common state data
|
|
|
|
* status - Interrupt status with error bits set
|
|
|
|
* oldstatus - Previous Interrupt status with error bits set
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_ERRORS
|
|
|
|
static void mcp2515_error(FAR struct can_dev_s *dev, uint8_t status,
|
|
|
|
uint8_t oldstatus)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv = dev->cd_priv;
|
|
|
|
struct can_hdr_s hdr;
|
|
|
|
uint8_t eflg;
|
|
|
|
uint8_t txerr;
|
|
|
|
uint8_t txb0err;
|
|
|
|
uint8_t txb1err;
|
|
|
|
uint8_t txb2err;
|
|
|
|
uint16_t errbits;
|
|
|
|
uint8_t data[CAN_ERROR_DLC];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Encode error bits */
|
|
|
|
|
|
|
|
errbits = 0;
|
|
|
|
memset(data, 0, sizeof(data));
|
|
|
|
|
|
|
|
/* Please note that MCP2515_CANINTF only reports if an error
|
|
|
|
* happened. It doesn't report what error it is.
|
|
|
|
* We need to check EFLG and TXBnCTRL to discover.
|
|
|
|
*/
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_EFLG, &eflg, 1);
|
|
|
|
if (eflg & EFLG_TXBO)
|
|
|
|
{
|
|
|
|
errbits |= CAN_ERROR_BUSOFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eflg & EFLG_RXEP)
|
|
|
|
{
|
|
|
|
data[1] |= CAN_ERROR1_RXPASSIVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eflg & EFLG_TXEP)
|
|
|
|
{
|
|
|
|
data[1] |= CAN_ERROR1_TXPASSIVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eflg & EFLG_RXWAR)
|
|
|
|
{
|
|
|
|
data[1] |= CAN_ERROR1_RXWARNING;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eflg & EFLG_TXWAR)
|
|
|
|
{
|
|
|
|
data[1] |= CAN_ERROR1_TXWARNING;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eflg & (EFLG_RX0OVR | EFLG_RX1OVR))
|
|
|
|
{
|
|
|
|
data[1] |= CAN_ERROR1_RXOVERFLOW;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Verify Message Error */
|
|
|
|
|
|
|
|
mcp2515_readregs(priv, MCP2515_TXB0CTRL, &txb0err, 1);
|
|
|
|
mcp2515_readregs(priv, MCP2515_TXB1CTRL, &txb1err, 1);
|
|
|
|
mcp2515_readregs(priv, MCP2515_TXB2CTRL, &txb2err, 1);
|
|
|
|
|
|
|
|
txerr = txb0err | txb1err | txb2err;
|
|
|
|
|
|
|
|
if (txerr & (TXBCTRL_MLOA))
|
|
|
|
{
|
|
|
|
errbits |= CAN_ERROR_LOSTARB;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (txerr & (TXBCTRL_ABTF))
|
|
|
|
{
|
|
|
|
errbits |= CAN_ERROR_LOSTARB;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (txerr & (TXBCTRL_MLOA))
|
|
|
|
{
|
|
|
|
data[0] |= CAN_ERROR0_UNSPEC;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((status & (MCP2515_INT_ERR | MCP2515_INT_MERR)) != 0)
|
|
|
|
{
|
|
|
|
/* If Message Error or Other error */
|
|
|
|
|
|
|
|
errbits |= CAN_ERROR_CONTROLLER;
|
|
|
|
}
|
|
|
|
else if ((oldstatus & (MCP2515_INT_ERR | MCP2515_INT_MERR)) != 0)
|
|
|
|
{
|
|
|
|
errbits |= CAN_ERROR_CONTROLLER;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (errbits != 0)
|
|
|
|
{
|
|
|
|
/* Format the CAN header for the error report. */
|
|
|
|
|
|
|
|
hdr.ch_id = errbits;
|
|
|
|
hdr.ch_dlc = CAN_ERROR_DLC;
|
|
|
|
hdr.ch_rtr = 0;
|
|
|
|
hdr.ch_error = 1;
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
hdr.ch_extid = 0;
|
|
|
|
#endif
|
|
|
|
hdr.ch_unused = 0;
|
|
|
|
|
|
|
|
/* And provide the error report to the upper half logic */
|
|
|
|
|
|
|
|
ret = can_receive(dev, &hdr, data);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
canerr("ERROR: can_receive failed: %d\n", ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_CAN_ERRORS */
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_receive
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Receive an MCP2515 messages
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - CAN-common state data
|
|
|
|
* rxbuffer - The RX buffer containing the received messages
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
#define RXREGVAL(reg) priv->spi_rxbuf[reg-MCP2515_RXB0CTRL]
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset)
|
|
|
|
{
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
struct can_hdr_s hdr;
|
|
|
|
int ret;
|
|
|
|
uint8_t regval;
|
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv);
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_readregs(priv, MCP2515_RXB0CTRL + offset, priv->spi_rxbuf,
|
|
|
|
SPI_TRANSFER_BUF_LEN);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDL);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_EXTID
|
|
|
|
if ((regval & RXBSIDL_IDE) != 0)
|
|
|
|
{
|
|
|
|
/* Save the extended ID of the newly received message */
|
|
|
|
|
|
|
|
/* EID7 - EID0 */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0EID0);
|
|
|
|
hdr.ch_id = regval ;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* EID15 - EID8 */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0EID8);
|
|
|
|
hdr.ch_id = hdr.ch_id | (regval << 8);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* EID17 and EID16 */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDL);
|
|
|
|
hdr.ch_id = hdr.ch_id | ((regval & RXBSIDL_EID_MASK) << 16);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* STD2 - STD0 */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
hdr.ch_id = hdr.ch_id | ((regval >> 5) << 18);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* STD10 - STD3 */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDH);
|
|
|
|
hdr.ch_id = hdr.ch_id | (regval << 21);
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_extid = true;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Save the standard ID of the newly received message */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDH);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_id = regval;
|
2019-04-12 19:37:08 +02:00
|
|
|
|
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDL);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_id = (hdr.ch_id << 3) | (regval >> 5);
|
|
|
|
hdr.ch_extid = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
if ((regval & RXBSIDL_IDE) != 0)
|
|
|
|
{
|
|
|
|
/* Drop any messages with extended IDs */
|
|
|
|
|
|
|
|
canerr("ERROR: Extended MSG in Standard Mode\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Save the standard ID of the newly received message */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDH);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_id = regval;
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0SIDL);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_id = (hdr.ch_id << 3) | (regval >> 5);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_ERRORS
|
|
|
|
hdr.ch_error = 0; /* Error reporting not supported */
|
|
|
|
#endif
|
|
|
|
hdr.ch_unused = 0;
|
|
|
|
|
|
|
|
/* Extract the RTR bit */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0CTRL);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_rtr = (regval & RXBCTRL_RXRTR) != 0;
|
|
|
|
|
|
|
|
/* Get the DLC */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
regval = RXREGVAL(MCP2515_RXB0DLC);
|
2017-05-23 19:28:52 +02:00
|
|
|
hdr.ch_dlc = (regval & RXBDLC_DLC_MASK) >> RXBDLC_DLC_SHIFT;
|
|
|
|
|
|
|
|
/* Save the message data */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
ret = can_receive(dev, &hdr, (FAR uint8_t *) & RXREGVAL(MCP2515_RXB0D0));
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
canerr("ERROR: can_receive failed: %d\n", ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_interrupt
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Common MCP2515 interrupt handler
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - CAN-common state data
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-03-20 14:48:40 +01:00
|
|
|
static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
|
|
|
|
FAR void *arg)
|
2017-05-23 19:28:52 +02:00
|
|
|
{
|
|
|
|
FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg;
|
|
|
|
FAR struct mcp2515_can_s *priv;
|
|
|
|
uint8_t ir;
|
|
|
|
uint8_t ie;
|
|
|
|
uint8_t pending;
|
2019-04-12 19:37:08 +02:00
|
|
|
uint8_t clrmask;
|
|
|
|
bool handled;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
priv = dev->cd_priv;
|
|
|
|
DEBUGASSERT(priv != NULL);
|
|
|
|
DEBUGASSERT(priv && priv->config);
|
|
|
|
|
|
|
|
/* Loop while there are pending interrupt events */
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
/* Get the set of pending interrupts. */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
mcp2515_read_2regs(priv, MCP2515_CANINTE, &ie, &ir);
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
pending = (ir & ie);
|
|
|
|
handled = false;
|
2019-04-12 19:37:08 +02:00
|
|
|
clrmask = 0;
|
|
|
|
|
|
|
|
if (pending == 0)
|
|
|
|
{
|
|
|
|
return OK;
|
|
|
|
}
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
/* Check for any errors */
|
|
|
|
|
|
|
|
if ((pending & MCP2515_ERROR_INTS) != 0)
|
|
|
|
{
|
|
|
|
/* Clear interrupt errors */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
pending &= ~MCP2515_ERROR_INTS;
|
|
|
|
clrmask |= MCP2515_ERROR_INTS;
|
2017-05-23 19:28:52 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_ERRORS
|
|
|
|
/* Report errors */
|
|
|
|
|
|
|
|
mcp2515_error(dev, pending & MCP2515_ERROR_INTS, priv->olderrors);
|
|
|
|
|
|
|
|
priv->olderrors = (pending & MCP2515_ERROR_INTS);
|
|
|
|
#endif
|
|
|
|
handled = true;
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_CAN_ERRORS
|
|
|
|
else if (priv->olderrors != 0)
|
|
|
|
{
|
|
|
|
/* All (old) errors cleared */
|
|
|
|
|
|
|
|
canerr("ERROR: CLEARED\n");
|
|
|
|
|
|
|
|
mcp2515_error(dev, 0, priv->olderrors);
|
|
|
|
|
|
|
|
priv->olderrors = 0;
|
|
|
|
handled = true;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Check for successful completion of a transmission */
|
|
|
|
|
|
|
|
if ((pending & MCP2515_TXBUFFER_INTS) != 0)
|
|
|
|
{
|
|
|
|
/* Clear the pending TX completion interrupt (and all
|
|
|
|
* other TX-related interrupts)
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (pending & MCP2515_INT_TX0)
|
|
|
|
{
|
|
|
|
caninfo("TX0 is empty to transmit new message!\n");
|
|
|
|
|
|
|
|
/* Clear TX0 interrupt */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
priv->txbuffers |= (1 << 0);
|
|
|
|
nxsem_post(&priv->txfsem);
|
|
|
|
pending &= ~MCP2515_INT_TX0;
|
|
|
|
clrmask |= MCP2515_INT_TX0;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pending & MCP2515_INT_TX1)
|
|
|
|
{
|
|
|
|
caninfo("TX1 is empty to transmit new message!\n");
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
priv->txbuffers |= (1 << 1);
|
|
|
|
nxsem_post(&priv->txfsem);
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Clear TX1 interrupt */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
pending &= ~MCP2515_INT_TX1;
|
|
|
|
clrmask |= MCP2515_INT_TX1;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pending & MCP2515_INT_TX2)
|
|
|
|
{
|
|
|
|
caninfo("TX2 is empty to transmit new message!\n");
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
priv->txbuffers |= (1 << 2);
|
|
|
|
nxsem_post(&priv->txfsem);
|
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
/* Clear TX2 interrupt */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
pending &= ~MCP2515_INT_TX2;
|
|
|
|
clrmask |= MCP2515_INT_TX2;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
handled = true;
|
|
|
|
|
|
|
|
#ifdef CONFIG_CAN_TXREADY
|
|
|
|
/* Inform the upper half driver that we are again ready to accept
|
|
|
|
* data in mcp2515_send().
|
|
|
|
*/
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
can_txready(dev);
|
2017-05-23 19:28:52 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else if ((pending & priv->txints) != 0)
|
|
|
|
{
|
|
|
|
/* Clear unhandled TX events */
|
|
|
|
|
|
|
|
handled = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if there is a new message to read */
|
|
|
|
|
|
|
|
if ((pending & MCP2515_RXBUFFER_INTS) != 0)
|
|
|
|
{
|
|
|
|
/* RX Buffer 0 is the "high priority" buffer: We will process
|
|
|
|
* all messages in RXB0 before processing any message from RX
|
|
|
|
* RXB1.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if ((pending & MCP2515_INT_RX0) != 0)
|
|
|
|
{
|
|
|
|
mcp2515_receive(dev, MCP2515_RX0_OFFSET);
|
|
|
|
|
|
|
|
/* Clear RX0 interrupt */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
pending &= ~MCP2515_INT_RX0;
|
|
|
|
clrmask |= MCP2515_INT_RX0;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if ((pending & MCP2515_INT_RX1) != 0)
|
|
|
|
{
|
|
|
|
mcp2515_receive(dev, MCP2515_RX1_OFFSET);
|
|
|
|
|
|
|
|
/* Clear RX1 interrupt */
|
|
|
|
|
2019-04-12 19:37:08 +02:00
|
|
|
pending &= ~MCP2515_INT_RX1;
|
|
|
|
clrmask |= MCP2515_INT_RX1;
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Acknowledge reading the FIFO entry */
|
2017-05-23 20:22:49 +02:00
|
|
|
|
2017-05-23 19:28:52 +02:00
|
|
|
handled = true;
|
|
|
|
}
|
2019-04-12 19:37:08 +02:00
|
|
|
|
|
|
|
mcp2515_modifyreg(priv, MCP2515_CANINTF, clrmask, pending);
|
2017-05-23 19:28:52 +02:00
|
|
|
}
|
|
|
|
while (handled);
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: mcp2515_hw_initialize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
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* MCP2515 hardware initialization
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*
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2018-02-01 17:00:02 +01:00
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* Input Parameters:
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2019-03-20 14:48:40 +01:00
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* priv - A pointer to the private data structure for this MCP2515
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* peripheral
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2017-05-23 19:28:52 +02:00
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int mcp2515_hw_initialize(struct mcp2515_can_s *priv)
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{
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FAR struct mcp2515_config_s *config = priv->config;
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uint8_t regval;
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caninfo("CAN%d\n", config->devid);
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2017-05-24 00:41:58 +02:00
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UNUSED(config);
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2017-05-23 19:28:52 +02:00
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/* Setup CNF1 register */
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mcp2515_readregs(priv, MCP2515_CNF1, ®val, 1);
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2019-03-20 14:48:40 +01:00
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regval = (regval & ~CNF1_BRP_MASK) |
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(MCP2515_BRP << CNF1_BRP_SHIFT);
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regval = (regval & ~CNF1_SJW_MASK) |
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((MCP2515_SJW - 1) << CNF1_SJW_SHIFT);
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2017-05-23 19:28:52 +02:00
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mcp2515_writeregs(priv, MCP2515_CNF1, ®val, 1);
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/* Setup CNF2 register */
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mcp2515_readregs(priv, MCP2515_CNF2, ®val, 1);
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2019-03-20 14:48:40 +01:00
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regval = (regval & ~CNF2_PRSEG_MASK) |
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((MCP2515_PROPSEG - 1) << CNF2_PRSEG_SHIFT);
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regval = (regval & ~CNF2_PHSEG1_MASK) |
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((MCP2515_PHSEG1 - 1) << CNF2_PHSEG1_SHIFT);
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2017-05-23 19:28:52 +02:00
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regval = (regval | CNF2_SAM | CNF2_BTLMODE);
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mcp2515_writeregs(priv, MCP2515_CNF2, ®val, 1);
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/* Setup CNF3 register */
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mcp2515_readregs(priv, MCP2515_CNF3, ®val, 1);
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2019-03-20 14:48:40 +01:00
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regval = (regval & ~CNF3_PHSEG2_MASK) |
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((MCP2515_PHSEG2 - 1) << CNF3_PHSEG2_SHIFT);
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2017-05-23 19:28:52 +02:00
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regval = (regval | CNF3_SOF);
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mcp2515_writeregs(priv, MCP2515_CNF3, ®val, 1);
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/* Mask all messages to be received */
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mcp2515_readregs(priv, MCP2515_RXB0CTRL, ®val, 1);
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2019-03-20 14:48:40 +01:00
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regval = (regval & ~RXBCTRL_RXM_MASK) |
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(RXBCTRL_RXM_ALLVALID << RXBCTRL_RXM_SHIFT);
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2017-05-23 19:28:52 +02:00
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regval = (regval | RXB0CTRL_BUKT); /* Enable Rollover from RXB0 to RXB1 */
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mcp2515_writeregs(priv, MCP2515_RXB0CTRL, ®val, 1);
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mcp2515_readregs(priv, MCP2515_RXB1CTRL, ®val, 1);
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2019-03-20 14:48:40 +01:00
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regval = (regval & ~RXBCTRL_RXM_MASK) |
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(RXBCTRL_RXM_ALLVALID << RXBCTRL_RXM_SHIFT);
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2017-05-23 19:28:52 +02:00
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mcp2515_writeregs(priv, MCP2515_RXB1CTRL, ®val, 1);
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regval = 0x00;
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mcp2515_writeregs(priv, MCP2515_RXM0SIDH, ®val, 1);
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mcp2515_writeregs(priv, MCP2515_RXM0SIDL, ®val, 1);
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#ifdef CONFIG_CAN_EXTID
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mcp2515_writeregs(priv, MCP2515_RXM0EID8, ®val, 1);
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mcp2515_writeregs(priv, MCP2515_RXM0EID0, ®val, 1);
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#endif
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mcp2515_writeregs(priv, MCP2515_RXM1SIDH, ®val, 1);
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mcp2515_writeregs(priv, MCP2515_RXM1SIDL, ®val, 1);
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#ifdef CONFIG_CAN_EXTID
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mcp2515_writeregs(priv, MCP2515_RXM1EID8, ®val, 1);
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mcp2515_writeregs(priv, MCP2515_RXM1EID0, ®val, 1);
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#endif
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#ifdef CONFIG_CAN_EXTID
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mcp2515_modifyreg(priv, MCP2515_RXM0SIDL, RXFSIDL_EXIDE, RXFSIDL_EXIDE);
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mcp2515_modifyreg(priv, MCP2515_RXM1SIDL, RXFSIDL_EXIDE, RXFSIDL_EXIDE);
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#endif
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/* Leave the Configuration mode, Move to Normal mode */
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mcp2515_readregs(priv, MCP2515_CANCTRL, ®val, 1);
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regval = (regval & ~CANCTRL_REQOP_MASK) | (CANCTRL_REQOP_NORMAL);
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mcp2515_writeregs(priv, MCP2515_CANCTRL, ®val, 1);
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2017-10-06 18:15:01 +02:00
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nxsig_usleep(100);
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2017-05-23 19:28:52 +02:00
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/* Read the CANINTF */
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mcp2515_readregs(priv, MCP2515_CANINTF, ®val, 1);
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caninfo("CANINFT = 0x%02X\n", regval);
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#ifdef MCP2515_LOOPBACK
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/* Is loopback mode selected for this peripheral? */
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if (config->loopback)
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{
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/* To Be Implemented */
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}
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#endif
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/* Configure interrupt lines */
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/* Select RX-related interrupts */
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priv->rxints = MCP2515_RXBUFFER_INTS;
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/* Select TX-related interrupts */
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priv->txints = MCP2515_TXBUFFER_INTS;
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2019-10-28 15:02:15 +01:00
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/* In this option we set a special receive mode in the
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* RXM[1:0] bits (RXBnCTRL[6:5]). In both registers:
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* RXB0CTRL and RXB1CTRL.
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* 11 = Turns mask/filters off; receives any message.
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*
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* In this mode it is tested that it receives both
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* extended and standard id messages.
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*/
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#ifdef CONFIG_CAN_EXTID
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mcp2515_readregs(priv, MCP2515_RXB0CTRL, ®val, 1);
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regval &= ~RXBCTRL_RXM_ALLMSG;
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regval |= RXBCTRL_RXM_ALLMSG;
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mcp2515_writeregs(priv, MCP2515_RXB0CTRL, ®val, 1);
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mcp2515_readregs(priv, MCP2515_RXB1CTRL, ®val, 1);
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regval &= ~RXBCTRL_RXM_ALLMSG;
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regval |= RXBCTRL_RXM_ALLMSG;
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mcp2515_writeregs(priv, MCP2515_RXB1CTRL, ®val, 1);
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#endif
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2017-05-23 19:28:52 +02:00
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: mcp2515_instantiate
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*
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* Description:
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* Initialize the selected MCP2515 CAN Bus Controller over SPI
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*
|
2018-02-01 17:00:02 +01:00
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* Input Parameters:
|
2017-05-23 19:28:52 +02:00
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* config - The configuration structure passed by the board.
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*
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* Returned Value:
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* Valid CAN device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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2019-03-20 14:48:40 +01:00
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FAR struct mcp2515_can_s *
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mcp2515_instantiate(FAR struct mcp2515_config_s *config)
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2017-05-23 19:28:52 +02:00
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{
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FAR struct mcp2515_can_s *priv;
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uint8_t canctrl;
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caninfo("Starting mcp2515_instantiate()!\n");
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2020-03-31 23:19:07 +02:00
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priv = (FAR struct mcp2515_can_s *)
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kmm_malloc(sizeof(struct mcp2515_can_s));
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2017-05-23 19:28:52 +02:00
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if (priv == NULL)
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{
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canerr("ERROR: Failed to allocate instance of mcp2515_can_s!\n");
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return NULL;
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}
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/* Setup SPI frequency and mode */
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2019-04-12 19:37:08 +02:00
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SPI_SETFREQUENCY(config->spi, CONFIG_MCP2515_SPI_SCK_FREQUENCY);
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2017-05-23 19:28:52 +02:00
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SPI_SETMODE(config->spi, MCP2515_SPI_MODE);
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SPI_SETBITS(config->spi, 8);
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2020-01-02 17:49:34 +01:00
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SPI_HWFEATURES(config->spi, 0);
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2017-05-23 19:28:52 +02:00
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/* Perform one time data initialization */
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memset(priv, 0, sizeof(struct mcp2515_can_s));
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priv->config = config;
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2019-04-12 19:37:08 +02:00
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priv->spi_txbuf = kmm_zalloc(SPI_TRANSFER_BUF_LEN);
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priv->spi_rxbuf = kmm_zalloc(SPI_TRANSFER_BUF_LEN);
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2017-05-23 19:28:52 +02:00
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/* Set the initial bit timing. This might change subsequently
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* due to IOCTL command processing.
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*/
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/* Initialize semaphores */
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2017-10-03 20:51:15 +02:00
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nxsem_init(&priv->locksem, 0, 1);
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2019-04-12 19:37:08 +02:00
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nxsem_init(&priv->txfsem, 0, MCP2515_NUM_TX_BUFFERS);
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/* Initialize bitmask */
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priv->txbuffers = (1 << MCP2515_NUM_TX_BUFFERS)-1;
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2017-05-23 19:28:52 +02:00
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/* And put the hardware in the initial state */
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mcp2515_reset_lowlevel(priv);
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/* Probe the MCP2515 to confirm it was detected */
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mcp2515_readregs(priv, MCP2515_CANCTRL, &canctrl, 1);
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if (canctrl != DEFAULT_CANCTRL_CONFMODE)
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{
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canerr("ERROR: CANCTRL = 0x%02X ! It should be 0x87\n", canctrl);
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return NULL;
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}
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/* Return our private data structure as an opaque handle */
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2017-06-14 17:38:58 +02:00
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return priv;
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2017-05-23 19:28:52 +02:00
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}
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/****************************************************************************
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* Name: mcp2515_initialize
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*
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* Description:
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* Initialize the selected MCP2515 CAN Bus Controller over SPI
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*
|
2018-02-01 17:00:02 +01:00
|
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* Input Parameters:
|
2017-05-23 19:28:52 +02:00
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* config - The configuration structure passed by the board.
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*
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* Returned Value:
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* Valid CAN device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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2020-03-31 23:19:07 +02:00
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FAR struct can_dev_s *mcp2515_initialize(
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FAR struct mcp2515_can_s *mcp2515can)
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2017-05-23 19:28:52 +02:00
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{
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FAR struct can_dev_s *dev;
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caninfo("Starting mcp2515_initialize()!\n");
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/* Allocate a CAN Device structure */
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2019-03-20 13:33:23 +01:00
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dev = (FAR struct can_dev_s *)kmm_zalloc(sizeof(struct can_dev_s));
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2017-05-23 19:28:52 +02:00
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if (dev == NULL)
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{
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canerr("ERROR: Failed to allocate instance of can_dev_s!\n");
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return NULL;
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}
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dev->cd_ops = &g_mcp2515ops;
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dev->cd_priv = (FAR void *)mcp2515can;
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return dev;
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}
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#endif /* CONFIG_CAN && CONFIG_MCP2515 */
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