Commit Graph

100 Commits

Author SHA1 Message Date
hujun5
0f243bde33 arch: fix the issue of asynchronous signal processing
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-08 09:11:14 +02:00
hujun5
6bf989159e system/signal: in interrupting the context, regs modify logic error
In the interrupt context, we should first save the interrupt context and modify the interrupt register
to execute the signal processing program immediately after exiting the current interrupt

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-07 20:33:46 +08:00
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00
zhangyuan21
884be2bdb9 assert: Distinguish between assert and exception
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-03 14:49:32 +08:00
hujun5
6063c0516e cpu: in SMP pthread_cancel occasionally deadlock
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-23 23:33:09 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
zhangyuan21
dfcba925e7 arch/arm64: add cache enable and disable function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
652fc7648e arch/arm64: Fixed error in getting cache size when there was no mmu
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
41f83a0271 arch/arm64: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
hujun5
ab0b3336c4 arch/arm64:Suppot tickless mode
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c

2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON

3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.

4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead

5 In arm64_tick_cancel func,The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles

6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-22 01:08:04 +08:00
zhangyuan21
c00498c164 arch/arm: update running task when context switch occurred
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:

1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
   and the running task obtained is still task1, but
   the actual task that generated the exception is task2.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 10:14:05 +09:00
zhangyuan21
f5f0af4f9c arch/arm64: fixed backtrace skip calc error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
2c599bb9e6 arch/arm64: call PANIC in arm64_fatal_error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
e4ae2b48b8 arch/arm64: Obtaining the correct fp pointer
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
zhangyuan21
c239d19df0 nuttx: add more dependent header file
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 09:13:32 +03:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
ligd
bb281eedfa cache: add up_get_xcache_linesize() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-03-20 17:17:22 +08:00
qinwei1
e3f0f86514 arm64: add arm64_serialinit/arm64_earlyserialinit
Summary:

   add arm64_serialinit/arm64_earlyserialinit function prototype
to arm64_internal.h as common function for arm64 based chip.
   Testing with ostest in SP and SMP

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-05 09:44:51 +08:00
Xiang Xiao
454921eac7 arch/boards: Rename up_lowputc to [arm64|renesas]_lowputc
follow other arch coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-04 11:08:00 +02:00
qinwei1
d2d954f691 arm64: ARMv8-r(Cortex-R82) support( add FVP platform )
Summary:
   Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:

 - GICv3 interrupt controllers for ARMv8-r
 - PL011 UART controller(FVP)

Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
  board readme.txt

TODO: merge PL011 UART driver to common place

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-02 13:33:15 +08:00
qinwei2004
fa359e355c Update arm64_head.S 2023-03-01 13:23:48 +08:00
qinwei1
518eb4076e arm64: ARMv8-r(Cortex-R82) support(mpid fix)
Summary
  Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
d5c6b8a94b arm64: add 64-bit time for all arm64 platform
Summary
  For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4cb5ff3353 arm64: ARMv8-r(Cortex-R82) support(add ARCH_SET_VMPIDR_EL2 option)
Summary

   VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
  So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
  identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
  every CPU at boot EL2 stage.
  For some platform, the bootloader or hypervisor will do that at
  the EL2 stage, but not all.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
0841f4dbaa arm64: ARMv8-r(Cortex-R82) support
Summary:

  Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:

1. ARM Single Security State Support, ARMv8-R support only single
   security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
   and system register for EL3 is not accessible(gcc will failed when
   access these registers)
3. add base MPU configure for the platform.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4240723b78 arm64: add ARCH_EARLY_PRINT support
Summary:
  The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
e5564a9872 arm64: PSCI config support
Summory
   This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
  Add configure option for it.

Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
chao an
3a0fdb019d nuttx: replace all ARRAY_SIZE()/ARRAYSIZE() to nitems()
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:05:44 +08:00
Ville Juven
9ac3e841da group_addrenv: Fix call to group_addrenv for targets that don't need it 2023-02-09 00:14:52 +08:00
Ville Juven
f4b82b6405 sched/addrenv: Remove up_addrenv_restore
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.

Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
2023-02-08 02:51:23 +08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
Gustavo Henrique Nihei
e6b204f438 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-01 23:47:44 +08:00
yinshengkai
3f97a87162 tools: add separate flags parameter for COMPILE/COMPILEXX
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-31 13:42:33 +08:00
qinwei1
b989e4f3a6 arch:arm64: add support for nuttx arm64 Toolchain Selection
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
   the opton to be configured with menuconfig

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-01-29 14:37:16 +08:00
Ville Juven
42d0e356c2 arch/addrenv: Change group_addrenv_t to arch_addrenv_t
This is preparation for moving address environments out of the group
structure into the tcb.

Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
2023-01-27 23:17:01 +08:00
Ville Juven
686b990a85 arch/ARCH_KERNEL_STACK: Fix signal handling with kernel stack
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
  This is fixed by making a stack frame to the user stack and copying it
  there.
- If the signal handler uses a system call, the kernel stack was completely
  and unconditionally destroyed, resulting in a crash in the user application

There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
2023-01-26 20:41:42 +08:00
Xiang Xiao
d7ee492fc4 board/arch: Remove FAR decorator
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-25 13:05:07 +02:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++??
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 15:41:57 +02:00
Jukka Laitinen
70de321de3 arch/Kconfig: remove virtual memory allocator dependency from MM_SHM
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.

Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-13 02:20:13 +08:00
Lee Lup Yuen
6d70b91a55 arm64/a64: Fix PIO Interrupt
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).

### Modified Files

`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt

`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH

`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
2023-01-06 13:43:44 +08:00
zouboan
7e81dce71c arm64/a64: add driver for Allwinner A64 I2C bus
arm64/a64: add driver for Allwinner A64 I2C bus

arm64/a64: add driver for Allwinner A64 I2C bus

arm64/a64: add driver for Allwinner A64 I2C bus
2023-01-03 01:45:56 +08:00
Lee Lup Yuen
17639af0a8 arm64/pinephone: Add driver for LCD Panel (Xingbangda XBD599)
This PR adds the driver for Xingbangda XBD599 LCD Panel (based on Sitronix ST7703 LCD Controller) on PINE64 PinePhone. This PR also includes:

- The driver for X-Powers AXP803 Power Mgmt IC, which calls our driver for Allwinner A64's Reduced Serial Bus. The PMIC Driver is needed to power on the MIPI DSI Interface for the LCD Panel.

- A simple Display Driver that renders a Test Pattern on the LCD Display at startup. It calls our Allwinner A64 drivers for Display Engine, Timing Controller TCON0 and MIPI Display Serial Interface.

The NuttX Frame Buffer Driver will be implemented in the next PR.

`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Changed the Frame Buffer pointer to `const` for Allwinner A64 Display Engine

`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for PWM, for controlling the PWM Backlight

`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Call `fb_register()` to start the Display Driver at startup

`boards/arm64/a64/pinephone/src/Makefile`: Added LCD Driver, PMIC Driver and Display Driver to Makefile

`boards/arm64/a64/pinephone/Kconfig`: Added the Kconfig option for "PINE64 PinePhone > LCD Display" (`CONFIG_PINEPHONE_LCD`) which enables the LCD Driver, PMIC Driver and Display Driver

`boards/arm64/a64/pinephone/src/pinephone_lcd.c`, `pinephone_lcd.h`: Driver for Xingbangda XBD599 LCD Panel

`boards/arm64/a64/pinephone/src/pinephone_pmic.c`, `pinephone_pmic.h`: Driver for X-Powers AXP803 Power Mgmt IC

`boards/arm64/a64/pinephone/src/pinephone_display.c`: Simple Display Driver that renders a Test Pattern in `up_fbinitialize()`

`boards/arm64/a64/pinephone/configs/lcd/defconfig`: New PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver (`CONFIG_PINEPHONE_LCD`)

`platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver
2022-12-27 11:44:17 +08:00
Xiang Xiao
b9d7d00943 arch: Remove the unused arch color function variant
up_check_tcbstack_remain, up_check_stack, up_check_stack_remain and up_check_intstack_remain

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-24 22:40:52 +02:00
zhangyuan21
45394eb6dc arch: save user context in assert common code
This is the work continue with #7875

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-24 13:02:56 +08:00