Commit Graph

21064 Commits

Author SHA1 Message Date
Petro Karashchenko
075738cf14 net/ip: print ip addresses using ip4_addrN macro
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-19 13:28:21 -03:00
Tiago Medicci Serrano
382debc996 esp32_c3_s3/wifi_ble: Use nxsem_trywait to take semphr from ISR
Use the non-blocking `nxsem_trywait` to try to take the semaphore
during the interrupt handler.
2023-08-19 18:40:31 +08:00
chenrun1
709301cbfd hostfs:support SEEK_CUR
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2023-08-19 01:48:48 +08:00
liaoao
c31e869fac cpuinfo: show cpufreq when hardware perfermance counting enabled
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-19 01:40:10 +08:00
Jukka Laitinen
f5575479f3 arch/risc-v/src/mpfs: Clean up BCLKSCLK training
This adds a config flag to remove manual bclksclk training if one wants
to just use the controller's own training.

Manual addcmd training depends on the manual bclksclk training, so this
also adds this dependency in Kconfig.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
Jukka Laitinen
bcfa6a8c5d arch/risc-v/src/mpfs/mpfs_ddr.c: Remove unused fields in mpfs_ddr_priv_s
There are leftover unused parameters in mpfs_ddr_priv_s. Just remove them.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
Jukka Laitinen
340ae8c753 arch/risc-v/src/mpfs/mpfs_ddr.c: Simplify code performing write calibration
This keeps the same functionality, the original code is just overly complicated

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
simbit18
70ab01a20b Fix Kconfig style
Replace help => ---help---
Remove spaces from Kconfig
Add comments
2023-08-18 16:36:04 +03:00
Lucas Saavedra Vaz
e02b203311 arch/xtensa/esp32s3: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
Lucas Saavedra Vaz
4bcc930535 arch/xtensa/esp32s2: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
Lucas Saavedra Vaz
60fdc9cb72 arch/xtensa/esp32: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
yanghuatao
aa34885c8b arch/arm: Fix arm_backtrace_unwind.c -Wmaybe-uninitialized and -Wint-conversion warning on n606
(1)common/arm_backtrace_unwind.c:528:18: warning: 'ctrl.lr_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
(2)common/arm_backtrace_unwind.c:626:27: warning: assignment to 'long unsigned int' from 'uint8_t (*)[]' {aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-08-18 12:20:21 +08:00
Jukka Laitinen
6a5d00f68c arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-17 17:50:37 +08:00
Jukka Laitinen
cd9ac3cf70 arch/risc-v/src/mpfs/mpfs_ddr.c: Don't continue training process if "verify" step fails
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-17 17:50:37 +08:00
Stuart Ianna
34bfa2f7ba arch/risc-v/litex: Add platform specific tickless implementation.
Adds a platform specific implementation for tickless schedular operation. This includes:
 - Tickless operation for vexriscv cores.
 - Tickless operation for vexriscv-smp cores.
 - Ticked operation for vexriscv-smp cores.

Ticked operation for vexriscv core has been refactored.

Additional default configuration added to demonstrate operation.

Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
2023-08-16 16:59:27 +08:00
Ryan MacDonald
074cf51268 Fix: s32k1 s32k3 kinetis: add propseg to ctrl1 timing mask 2023-08-16 10:09:40 +03:00
Tiago Medicci Serrano
5adb9de00b espressif: Update esp-hal-3rdparty version
The newest version of the esp-hal-3rdparty includes general
bugfixes and includes components necessary to build the IDFboot.
2023-08-15 13:39:22 -03:00
wangming9
e953715e6d arch/arm: add qemu support for ARM32
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-15 23:56:41 +08:00
yinshengkai
88f3bc77f1 toolchain: detect use of large stack variables
partition/fs_gpt.c:384:5: warning: stack usage might be 288 bytes [-Wstack-usage=]
  384 | int parse_gpt_partition(FAR struct partition_state_s *state,

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-08-15 14:50:27 +03:00
Tiago Medicci Serrano
281ab83309 esp32s3: Use PANIC() instead of assert(0)
Considering kernel code, it's reasonable to use `PANIC()` instead
of `assert(0)` to handle with situations that require abort. Unlike
`assert`, `PANIC()` doesn't dependent on `NDEBUG`.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
01b6c87b15 esp32s3: Implement the Wi-Fi/BLE coexistence
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
7d605551cd esp32s3/wifi: Enable peripheral interrupt to the same CPU interrupt
The low-level Wi-Fi driver registers two peripheral interrupts to
the same CPU interrupt. Although the registered ISR is the same for
both peripherals interrupt, it's needed to call `up_enable_irq` to
ensure that the interrupt matrix is being set accordingly.

Please note that the current implementation of the  ESP32-S3's IRQ
driver - although allow us to set a callback for each IRQ, which
represents the peripherals interrupt - doesn't allow us to call
both callbacks when these IRQs refers to a same CPU interrupt.
`g_cpu0_intmap` (or `g_cpu1_intmap`) associates each CPU interrupt
to a single IRQ/peripheral and, then, when a CPU interrupt is
triggered, only the last registered IRQ's callback will be called.
This isn't a problem here because 1) the registered callback is the
same for both IRQ's (in fact, it considers the CPU interrupt) and
2) we know in advance which peripheral interrupts will be attached
to which CPU interrupt and, then, we can set them directly.
2023-08-14 16:29:21 -03:00
Petro Karashchenko
655d00b1e7 arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
33f03fc98c esp32s3/wlan: Always run wlan_rxpoll work queue
Even if we were unable to get a free IOB, trigger the work queue
to make sure that no old packet is waiting to be handled by the
network upper layers.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
012dddf7c9 esp32s3/wlan: check for all connections on wlan_txpoll
This prevents us from getting stuck while polling the different
network structures in `devif_poll_connections`. This is useful for
Wi-Fi/Bluetooth coexistence, specifically.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
6589887284 esp32s3/wlan: check if the network device's IOB isn't null
Before adding the upper layer network device's IOB to the TX queue
of the wireless driver, check if it isn't null.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
ec4149c61d esp32s3/hardware: Update regi2c_ctrl.h functions name 2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
6089f58f00 esp32s3/irq: Enhance IRQ subsystem
- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
31476bcb34 esp32s3/rtc: Initialize RTC subsystem
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
7dafbb05a1 esp32s3/peripherals: Add initialization routine for the peripherals
It provides an initialization function that performs the
peripherals' initialization routine during the chip startup.
2023-08-14 16:29:21 -03:00
Xiang Xiao
14563aa48c arch/armv7r: Sync gic/timer with armv7-a and armv8-a
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
Xiang Xiao
e4dea90725 arch/armv7-a: Update the macro definition in gic.h
https://developer.arm.com/documentation/ihi0048/b

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
raiden00pl
89174e6a1a arch/stm32h7: use correct name for bit 2 in STM32_PWR_CR3 register 2023-08-14 23:42:37 +08:00
David Sidrane
60840f1ed2 imxrt:Serial Preserve all but W1C bit in SR
SR contains configuration bits that need to be preserved.
2023-08-14 18:23:59 +03:00
raiden00pl
b73e1b9591 arch/{nrf52|nrf53|nrf91}: handle I2C errors in interrupt mode 2023-08-14 17:51:48 +08:00
raiden00pl
5572552024 arch/nrf53: port 6e8f25ba3b change from nrf52
Added config setting for NRF53 I2C timing bug workaround
2023-08-13 11:45:06 -03:00
raiden00pl
eec59015f0 arch/{nrf53|nrf91}: port cc99d94cfd change from nrf52
Fixed NRF52 I2C register naming
2023-08-13 11:45:06 -03:00
raiden00pl
3a61db4c7b arch/nrf53: port d7aea88727 change from nrf52
Changed NRF53 USB initialization to check for power via USBREGSTATUS instead of waiting for interrupt
2023-08-13 11:45:06 -03:00
raiden00pl
fc4ddfb1f4 arch/nrf52/nrf52_twi.h: fix condition
missing prefix CONFIG_* in commit 6e8f25ba3b
2023-08-13 11:45:06 -03:00
raiden00pl
bcef7d32f5 arch/nrf52/nrf52_i2c.c: remove unnecessary include introduced in cc99d94cfd 2023-08-13 11:45:06 -03:00
simbit18
693b034827 arch/arm/src/nrf91/Kconfig: Fix Kconfig style
Add TABs
Add comments
Remove spaces from Kconfig file
2023-08-13 11:44:19 -03:00
Xiang Xiao
bd30d1a4d5 arch: Move trustzone related setting to common place
to share the security setting between arm32 and arm64

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
Xiang Xiao
b183114d43 arch/arm: Change the default value to ARCH_TRUSTZONE_NONSECURE
since nuttx normally run inside the non secure execution environment

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
Brian Doherty
d7aea88727 Changed NRF52 USB initialization to check for power via USBREGSTATUS instead of waiting for interrupt, in case we've been launched from a bootloader. 2023-08-13 06:47:14 +08:00
Brian Doherty
cc99d94cfd Fixed NRF52 I2C register naming. 2023-08-13 06:46:57 +08:00
Brian Doherty
6e8f25ba3b Added config setting for NRF52 I2C timing bug workaround. 2023-08-13 06:46:31 +08:00
wangming9
c928acc9ff perf: The new configuration supports hardware performance counting
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting,solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.

This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion

To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-12 02:20:44 +08:00
TimJTi
d0613fa165 SAMA5D2 MCAN Error corrections plus changes to improve clarity
Kconfig typo
2023-08-12 02:20:09 +08:00
David Sidrane
2dc6365e24 s32k3xx:lpi2c fix status handeling & race
s32k3:lpi2c:Simplify DMA and Non DMA usage

s32k3xx: lpi2c dma invalidate cache after exchange

s32k3xx:lpi2c fix timeout not stopping dma
2023-08-11 13:41:49 -03:00
David Sidrane
afdce6e8c2 imxrt:lpi2c fix status handeling & race
imxrt:lpi2c:Simplify DMA and Non DMA usage

imxrt: lpi2c dma invalidate cache after exchange

imxrt:lpi2c fix timeout not stopping dma
2023-08-11 13:41:49 -03:00