Commit Graph

736 Commits

Author SHA1 Message Date
YAMAMOTO Takashi
03c332acf0 arm: Add _intmax_t and _uintmax_t 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
e8a9ce4988 arm inttypes.h: Use long for 32-bit integer 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
b1ed95f29d arm: Change _int32_t from int to long to match the compiler 2020-11-19 00:49:56 -08:00
Nathan Hartman
87bfa24c8c stm32/stm32_spi: Add SPI register definitions for STM32G47XX
arch/arm/src/stm32/hardware/stm32_spi.h:

    * Avoid numerous ifdef on STM32 part numbers and make the
      different variations of SPI peripheral features more
      self-documenting: based on STM32_HAVE_IP_SPI_V* defines
      from chip.h, define some or all of HAVE_SPI_I2S,
      HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
      HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
      which registers and bitfields to define based on them.

    * Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
      currently used only for STM32G47XX family MCUs, including
      SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
      SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
      SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
      SPI_I2SCFGR_ASTRTEN.

    * SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
      (xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (1 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * Fix nxstyle errors.

arch/arm/include/stm32/chip.h:

    * Add new section "Peripheral IP versions" and specify version of
      SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
      STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
2020-11-12 04:37:32 -08:00
YAMAMOTO Takashi
178815ea34 arm inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
Frank-Christian Kruegel
52097a4345 Added Support for more TI Tiva Microcontrollers:
* TM4C123GH6PZ (100 pin version of TM4C123GH6PM)
* TM4C123GH6PGE (144 pin version of TM4C123GH6PM)
* TM4C129ENCPDT (TM4C1294 with Crypto hardware added, TQFP package)
* TM4C129ENCZAD (TM4C1294 with Crypto hardware added, BGA package)
2020-11-03 08:07:24 -08:00
Xiang Xiao
2956b8516b Fix nxstyle warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-10-20 01:45:06 -07:00
Xiang Xiao
eb4121ce38 Change all 'Nuttx' to 'NuttX'
Unify the naming convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-10-20 01:45:06 -07:00
raiden00pl
33901969fe Fix nxstyle warnings 2020-10-10 12:24:28 -06:00
raiden00pl
25c58f2a32 stm32f0l0g0: Changed headers for apache 2.0 license 2020-10-10 12:24:28 -06:00
Nathan Hartman
18edab3ad2 tiva: Fix nxstyle warnings
arch/arm/include/tiva/cc13x0_irq.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/cc13x2_cc26x2_irq.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/chip.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/irq.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/lm3s_irq.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/lm4f_irq.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/include/tiva/tm4c_irq.h:

    * Fix nxstyle warnings. No functional changes.
2020-10-09 15:35:38 +01:00
Daniel Agar
3df8f79111 stm32f412ce fixes 2020-09-22 22:44:43 -07:00
Xiang Xiao
d078518502 arch/arm: Should include arch/armv8-m/spinlock.h when CONFIG_ARCH_ARMV8M is defined
forget in commit 2376d8a266
Author: qiaowei <qiaowei@xiaomi.com>
Date:   Wed Apr 22 10:09:50 2020 +0800

    Porting arch/armv8-m support

    1. Add dsp extension; float point based on hardware and software.
    2. Delete folder "iar"
    3. Add tool chain for cortex-M23 and cortex-M35p

    Signed-off-by: qiaowei <qiaowei@xiaomi.com>
    Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-22 23:05:29 +01:00
Xiang Xiao
7faf72cabc arch/arm: Add ARCH_ARMV6M Kconfig to prepare the support of CortexM0+
also align with the armv7m implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-22 23:05:29 +01:00
raiden00pl
3241ebf811 arch/nrf52: remove redundant chip definitions from Kconfig 2020-08-31 11:49:49 -03:00
raiden00pl
45f3aa4ca9 arch/nrf52: replace all chip-specific conditions with chip-features conditions in all hardware definitions. This gives us a more modular code. 2020-08-31 11:49:49 -03:00
Johannes Schock
a32912040f Several nxstyle fixes. 2020-08-05 08:55:54 -03:00
Johannes Schock
c760db7fd0 Kinetis K28 USBHS USB-Host. 2020-08-05 08:55:54 -03:00
Masayuki Ishikawa
16cd363cb0 arch: lc823450: Replace license header with Apache License 2.0
Summary:
- This commit replaces license header under lc823450

Impact:
- No impact

Testing:
- Build check only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-08-03 21:03:41 +01:00
Masayuki Ishikawa
904ec767f7 arch: lc823450: Fix nxstyle violations
Summary:
- This PR fixes style violations for lc823450.
- NOTE: I will fix more style violations in separate PR later.

Impact:
- No impacts.

Testing:
- I checked build test only.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-07-28 06:07:31 -05:00
SPRESENSE
d560ce65ff cxd56xx: spresense: Add some improvements and fix bugs for Spresense board
- Add new functions of GNSS
- Support the lower PWM frequency
- Add CONFIG_CPUFREQ_RELEASE_LOCK
- Add high speed ADC support
- Add HPADC input gain configuration
- Add eMMC device
- Frame buffer support
- Fix SD/GNSS/sensor drivers not worked
- Build errors
- Fix nxstyle issues
2020-07-28 09:13:05 +02:00
Brennan Ashton
aef6f4ae09 Add initial support for the QuickLogic EOS S3
The QuickFeather board added as an initial target.
These featrues are minimally implemented:
  * Clock Configuration -- All clocking registers are defined and
    configuration is used to setup the HSO, M4 Core, and M4 Perif
    clocks.  Additionally some clock debugging is stubbed for
    bringing out clock paths to IO pins.

  * UART -- The lowputc as well as the serial driver is implemnted
    for the single UART device. Currently the configuration is
    hard coded, but uses the proper interfaces to later fill in.

  * SysTick -- The system tick timer is implemented and clocking
    properly. Tickless mode is not yet implemented.

  * Interrupts -- The interrupt system is implemented and verified
    using the UART and SysTick systems.

  * GPIO -- GPIO and IOMUX systems are defined and implemented.
    This is verified using the UART as well as the Arch LED
    system.  The GPIO interupt system is stubbed out but not
    implemented.

  * Arch LEDS -- The blue LED as part of the RGB LED is configured
    and attached to the Arch LED system.  This indicates the device
    coming online as well as when a hardfault is triggered.

Applications and Testing:
  * There is a nsh configuration implemented that includes debug
    features as well as the ostest, getprime, and mem test.
    All of these have been run and verified.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2020-07-15 11:25:30 +01:00
Xiang Xiao
05f6445493 arch: Move *_getsp to the common place arch/arch.h
so other place can get the stack pointer easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-07-09 13:51:09 +01:00
Jari van Ewijk
86c151edf1 S32K Small Fixes:
- Typos / wrong names in s32k14x_irq.h, s32k1xx_memorymap.h and s32k1xx_pcc.h
- Wrong base address for port input disable register in s32k1xx_pin.c
- up_* still had to be changed to arm_* in some places
2020-06-30 15:46:15 +01:00
Jacob Dahl
b12b3072e8 Added support for STM32F412xx. Tested with the NUCLEO-F412ZG dev board as well as a custom board using the STM32F412CE. 2020-06-29 17:44:35 +02:00
Xiang Xiao
4fbbd2e3bf arch: Move PRIxMAX and SCNxMAX definition to include/stdint.h
like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
2020-06-10 08:24:47 +02:00
Xiang Xiao
7758eb8658 arch: Define INTx_C and UINTx_C macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia50ea8764880fabd3d878c95328632c761be6b43
2020-06-10 08:24:47 +02:00
Alan C. Assis
d41a2f87f0 Add support to STM32F411CE 2020-06-07 02:29:16 +01:00
David Sidrane
bcf673a673 stm32h7 stm32h7x3xx_irq: Fix CS violation 2020-05-23 09:16:30 -03:00
David Sidrane
f5482b50ee stm32h7:stm32h7x3xx_irq STM32_IRQ_SDMMC->STM32_IRQ_SDMMC2 2020-05-23 09:16:30 -03:00
Nathan Hartman
168a4cafc6 Add support for STM32G474: Modify existing files
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.

This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.

arch/arm/Kconfig:
arch/arm/include/stm32/chip.h:
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/Kconfig:
arch/arm/src/stm32/hardware/stm32_adc.h:
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
arch/arm/src/stm32/hardware/stm32_dma.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_flash.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_i2c_v2.h:
arch/arm/src/stm32/hardware/stm32_memorymap.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/hardware/stm32_tim.h:
arch/arm/src/stm32/stm32_allocateheap.c:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dma_v1.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.c:
arch/arm/src/stm32/stm32_gpio.h:
arch/arm/src/stm32/stm32_lowputc.c:
arch/arm/src/stm32/stm32_rcc.c:
arch/arm/src/stm32/stm32_rcc.h:
arch/arm/src/stm32/stm32_serial.c:
arch/arm/src/stm32/stm32_syscfg.h:
arch/arm/src/stm32/stm32_uart.h:

    * Add architectural support to existing NuttX files. This
      makes the STM32G474 family parts accessible to the system.

With big thanks for detailed code review:
    David Sidrane (davids5)
    Mateusz Szafoni (raiden00)
    Abdelatif Guettouche (Ouss4)
2020-05-23 09:02:00 -03:00
Nathan Hartman
3b4e4c603f Add support for STM32G474: New files
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.

This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.

arch/arm/include/stm32/stm32g47xxx_irq.h:
arch/arm/src/stm32/hardware/stm32g474cxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474mxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474qxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474rxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474vxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h:
arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h:
arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h:
arch/arm/src/stm32/hardware/stm32g47xxx_syscfg.h:
arch/arm/src/stm32/hardware/stm32g47xxx_uart.h:
arch/arm/src/stm32/stm32g47xxx_rcc.c:

    * New files required for architectural support. Note that
      existing NuttX files are not modified. As such, in this
      revision, the system is unaffected by their addition.

With big thanks for detailed code review:
    David Sidrane (davids5)
    Mateusz Szafoni (raiden00)
    Abdelatif Guettouche (Ouss4)
2020-05-23 09:02:00 -03:00
Nathan Hartman
34286dfdac stm32: nxstyle fixes
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.h:

    * nxstyle fixes, mostly long lines
2020-05-20 11:23:48 +08:00
qiaowei
cddd64fd30 armv8-m: Add stack overflow by stack pointer limit register
Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I0f0ae0fb8edb8e1690b3c5e3e8b3189d51a318b0
2020-05-18 07:21:05 -06:00
Xiang Xiao
7ffafa3654 Remove executable bit from source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-13 06:32:13 -06:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
2020-05-07 12:04:16 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Gregory Nutt
bda24f09c2 libs/libc/tls/tls_getinfo.c: Add tls_get_info()
Move the logic to get TLS information from an inline function to a normal function.  For the unaligned case, it is probably too large to be inlined.

Also fixes some minor things from review of previous commits.
2020-05-05 18:56:33 +01:00
Abdelatif Guettouche
b7e7fba732 TLS_UNALIGNED (#2)
* Implement the TLS_UNALIGNED
2020-05-05 18:56:33 +01:00
Gregory Nutt
6766aa0ed5 Mea Culpa. Fix nxstyle problems from PR879
In a fit of confusion, I accidentally committed PR 879 before it passed its nxstyle check (it did pass all of its build tests, but not the style check).  It was really my intention to merge PR878, but I screwed that up and merged 879 instead.

This PR makes amends by passing all of the .c and .h files modified by PR879 through nxstyle and correcting all reported style problems.
2020-04-26 11:56:15 -03:00
qiaowei
2376d8a266 Porting arch/armv8-m support
1. Add dsp extension; float point based on hardware and software.
2. Delete folder "iar"
3. Add tool chain for cortex-M23 and cortex-M35p

Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7
2020-04-26 07:43:37 -06:00
Gregory Nutt
e6af32c88f Run nxstyle against all files modified by PR 848 2020-04-22 21:36:41 +01:00
Nathan Hartman
02ab0cd149 stm32: Fix typos, wrong comments, and nxstyle.
arch/arm/include/stm32/chip.h:

    * Fix 2 typos.

    * Fix 1 wrong comment (No LCD -> LCD)

    * Fix nxstyle errors regarding comment positions, blank lines
      before/after comments, and C++ style comments.
2020-04-22 16:14:57 +01:00
Alin Jerpelea
afead9c9da arch: arm: a1x: nxstyle fixes for a1x arch
nxstyle fixes for a1x arch

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2020-04-21 13:46:07 +08:00
Nathan Hartman
120de788d4 kinetis: Fix typos
arch/arm/include/kinetis/kinetis_pmc.h:

    * Fix several typos in comments.
    * Rewrap some comment lines.
    * Fix define KINETIS_PMC_VERSION_UKN: Put -1 in
      parenthesis for safety.
    * Fix nxstyle complaint regarding long line.
2020-04-16 14:43:54 -06:00
Nathan Hartman
9b9d1fc7ca arch/stm32h7: Extend support to all STM32H7x3xx
All parts in the STM32H7x3xx family have the same pinmap, etc.,
so extending support to all members of the family required only
minimal changes: Adding them to Kconfig, extending some
preprocessor logic, and minor code changes.

arch/arm/src/stm32h7/Kconfig:

    * Add explicit support for all microcontrollers in the
      STM32H7x3xx family by adding support for:
        - STM32H743AG
        - STM32H743AI
        - STM32H743BG
        - STM32H743BI
        - STM32H743IG
        - STM32H743II
        - STM32H743VG
        - STM32H743VI
        - STM32H743XG
        - STM32H743XI
        - STM32H743ZG
        - STM32H753AI
        - STM32H753BI
        - STM32H753VI
        - STM32H753XI
        - STM32H753ZI

    * Fix TODO items for IO_CONFIG (all STM32H7X3XX).

    * Because 100-pin parts lack GPIO ports F and G, but have
      port H, create the new hidden configs STM32H7_HAVE_GPIOF
      and STM32H7_HAVE_GPIOG.

    * STM32H7_STM32H7X3XX:
      - Select STM32H7_HAVE_GPIOF and STM32H7_HAVE_GPIOG only
        when not STM32H7_IO_CONFIG_V (100-pin part).
      - STM32H7_STM32H7X3XX: select STM32H7_HAVE_SPI5 for all
        IO configs except V (100-pin part), which doesn't expose
        SPI5 due to pin count.

    * STM32H7_STM32H7X7XX: Always select STM32H7_HAVE_GPIOF and
      STM32H7_HAVE_GPIOG because we aren't adding more part
      numbers in this family.

    * Remove extraneous (duplicate) "bool" and "default n"
      lines.

    * config STM32H7_FMC: Fix indent (contents were indented
      with spaces while rest of file uses tabs).

arch/arm/include/stm32h7/chip.h:

    * Extend preprocessor logic to add support for the new
      MCU part numbers.

    * Expand table of differences between family members.

    * Define STM32H7_NGPIO based on IO_CONFIGs decided in Kconfig.

    * If IO config is not known, issue compile-time #error
      with grep-friendly "CONFIG_STM32H7_IO_CONFIG_x Not Set."
      Suggested by davids5.

arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h:
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c:
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c:

    * When checking STM32H7_NGPIO > 5 or 6, check also
      CONFIG_STM32H7_HAVE_GPIOF or CONFIG_STM32H7_HAVE_GPIOG.

arch/arm/src/stm32h7/stm32_gpio.c:

    * stm32_configgpio(): When applicable, make sure we're not
      trying to configure one of the missing ports.

    * Fix nxstyle complains (wrong end of line comment position
      and several long lines). No functional changes.

    * g_gpiobase[]: Init base address for ports F and G according to
      CONFIG_STM32H7_HAVE_GPIOF and CONFIG_STM32H7_HAVE_GPIOG.

    * stm32_configgpio(): Replace complicated check with g_gpiobase[]
      null check. Suggested by davids5.

    * stm32_gpiowrite() and stm32_gpioread(): Add previously missing
      null check of g_gpiobase[].

arch/arm/src/stm32h7/stm32_gpio.h:

    * Wrap the defines GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD,
      GPIO_PORTE, GPIO_PORTF, GPIO_PORTG, GPIO_PORTH, GPIO_PORTI,
      GPIO_PORTJ, and GPIO_PORTK in conditional logic so that the
      compiler will prevent use of ports that do not exist on the
      target MCU.

    * Fix nxstyle complaints.

Documentation/NuttX.html:

    * Remove copy-and-pasted anchor for stm32f76xx77xx.

    * Correct link to README.txt for Nucleo-H743ZI board,
      formerly on BitBucket, now on GitHub.

    * Add list item for STMicro STM32H747I-DISCO board.

Co-Authored-By: David Sidrane <David.Sidrane@Nscdg.com>
2020-04-16 13:23:12 -06:00
Alin Jerpelea
222a3b9fe8 arch: arm: cxd56xx: nxstyle fixes
nxstyle fixes for cxd56xx

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2020-04-14 13:20:21 +01:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly
This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
raiden00pl
7135c91b0f arch/arm/include/xmc4: add irq definitions for xmc4700 and xmc4800 2020-03-22 08:29:51 -06:00
Andrey Zabolotnyi
e5f5509054
stm32h7: Added basic support for STM32H753II. (#527)
Co-authored-by: Андрей Заболотный <zapparello@ya.ru>
2020-03-10 07:55:18 -07:00