Gregory Nutt
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dd4be66f1c
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ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
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Gregory Nutt
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b57d2182ab
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ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly
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2014-07-26 18:48:54 -06:00 |
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Gregory Nutt
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6f5280d284
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ARMv7 L2 Cache: Minor bugfixes/improvements
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2014-07-26 18:48:26 -06:00 |
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Gregory Nutt
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ee59870325
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Enables cache early in boot-up sequence
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2014-07-26 18:48:00 -06:00 |
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Gregory Nutt
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4e146d2ec2
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Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled
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2014-07-26 18:47:33 -06:00 |
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Gregory Nutt
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873788bf5a
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New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled
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2014-07-26 18:46:52 -06:00 |
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Gregory Nutt
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2eb526253b
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Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place.
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2014-07-26 16:54:19 -06:00 |
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Gregory Nutt
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6d9ca195ee
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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
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2014-07-26 16:50:08 -06:00 |
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Gregory Nutt
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fcbf89c6f6
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ARMv7-A: L2CC PL310 address filtering is an optional feature
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2014-07-25 19:46:09 -06:00 |
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Gregory Nutt
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a007fa3f5e
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ARMv7-A: Add missing L2CC PL310 bit definitions
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2014-07-25 19:41:35 -06:00 |
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Gregory Nutt
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e74f37445b
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rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well.
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2014-07-25 17:25:17 -06:00 |
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Gregory Nutt
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2ec0ab3b5e
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3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN
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2014-07-24 16:51:07 -06:00 |
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Gregory Nutt
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1366ce0a02
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Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT
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2014-07-24 16:42:15 -06:00 |
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Gregory Nutt
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a3d20b2fa1
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LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max
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2014-07-24 16:39:18 -06:00 |
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Gregory Nutt
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dd74e75d1e
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Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max
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2014-07-24 16:23:31 -06:00 |
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Gregory Nutt
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21d67c5b1b
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Mostly cosmetic changes from Max
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2014-07-24 16:00:21 -06:00 |
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Gregory Nutt
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43a578d2d3
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Eliminate warnings. From Max
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2014-07-24 15:50:37 -06:00 |
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Gregory Nutt
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5e19807250
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Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max
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2014-07-24 15:37:13 -06:00 |
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Gregory Nutt
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949e002d76
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Fix a recently introduced typo that was being masked by some bad conditional compilation
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2014-07-22 11:45:14 -06:00 |
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Gregory Nutt
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d57c3b4e82
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Update ChangeLog
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2014-07-22 07:25:01 -06:00 |
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Gregory Nutt
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45c03e5a1a
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STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen
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2014-07-22 07:23:17 -06:00 |
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Gregory Nutt
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615b7d6c7a
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Fix typos in the STM32 DAC header file. From Petteri Aimonen
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2014-07-22 07:13:33 -06:00 |
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Gregory Nutt
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af8f5f4bdc
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SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this
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2014-07-21 17:46:35 -06:00 |
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Gregory Nutt
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4ce2e094ba
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SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled
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2014-07-21 17:45:48 -06:00 |
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Gregory Nutt
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80c0b5628d
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SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC
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2014-07-21 16:49:56 -06:00 |
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Gregory Nutt
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519c8f3e97
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SAMA5 XDMAC: Missing some CUBC bits
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2014-07-21 16:47:16 -06:00 |
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Gregory Nutt
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2d69c2f519
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SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete
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2014-07-21 13:24:55 -06:00 |
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Gregory Nutt
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c5b58b189c
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XDMAC register sampling missed CIM register; Should not set SWREQ bit in DMA setup
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2014-07-21 13:23:36 -06:00 |
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Gregory Nutt
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35ea8f1542
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Fix a commented out assertion
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2014-07-20 17:06:55 -06:00 |
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Gregory Nutt
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b207138be9
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Fix typos in comments
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2014-07-20 13:09:47 -06:00 |
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Gregory Nutt
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7ba2d9ed36
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SAMA5D4-EK: PIO Schmitt trigger logic backward
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2014-07-20 13:04:30 -06:00 |
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Gregory Nutt
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9392953ea1
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WM8904 w/NxPlayer: Fix some compile errors and warnings with debug enabled
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2014-07-20 09:17:36 -06:00 |
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Gregory Nutt
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7c56185006
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SAMA5D ADC: Fix some typos in conditional compilation
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2014-07-19 13:56:48 -06:00 |
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Gregory Nutt
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3c29703c42
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SAMA5 SCK: The SAMA5D3 does things a little differently
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2014-07-19 13:55:53 -06:00 |
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Gregory Nutt
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e82143ac38
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SAMA5 PCK: Add support for the slow clock as the PCK clock source
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2014-07-19 13:55:08 -06:00 |
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Gregory Nutt
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8986bd3976
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SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3
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2014-07-19 13:25:59 -06:00 |
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Gregory Nutt
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813eade679
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SAMA5: Add slow clock support
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2014-07-19 13:07:55 -06:00 |
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Gregory Nutt
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c7055a4cb8
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SAMA5D4-EK: Add WM8904 initialization logic
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2014-07-19 11:58:53 -06:00 |
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Gregory Nutt
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8055a59d49
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SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems
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2014-07-12 11:24:14 -06:00 |
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Gregory Nutt
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424d47cfee
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SAMA5D4-EK LCDC: Change source clock to 2*Mck seems to solve stability issues
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2014-07-12 09:45:05 -06:00 |
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Gregory Nutt
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30603b1021
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SAMA5D4-EK LCDC: Adding a delay after enabling the LCD solves lots of start-up timing issues
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2014-07-12 08:05:22 -06:00 |
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Gregory Nutt
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20493f1212
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Lpc17xx Ethernet: Comment out an assertion that is reported to first inappropriately. From Max
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2014-07-11 12:25:11 -06:00 |
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Gregory Nutt
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67468408ae
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SAMA5D4-EK LCD: Actual hardware with appears to be RGB888
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2014-07-10 12:23:41 -06:00 |
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Gregory Nutt
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c7d53cb927
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SAMA5D4-EK: LCDC works (with a few color problems)
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2014-07-10 12:03:10 -06:00 |
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Gregory Nutt
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6563ae07c2
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Don't have to set SDA high initially in I2C reset because that is done by the pin configuration
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2014-07-09 17:17:32 -06:00 |
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Gregory Nutt
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fc973eb512
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SAMA5 PIO: Fix a typo in Schmitt trigger configuration; Configure pin as a a vanilla input first so that final pin configuration is more read-able (i.e., easier to debug)
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2014-07-09 17:16:43 -06:00 |
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Gregory Nutt
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0d4255257d
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SAMA5 I2C Reset: More changes... still does not work right
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2014-07-09 15:09:06 -06:00 |
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Gregory Nutt
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c1ca11331d
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SAMA5 TWI: Some restructured needed by up_i2creset. Also timeout needs to vary with the size of the transfer and if debug is on or not
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2014-07-09 13:39:10 -06:00 |
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Gregory Nutt
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ee351dc695
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Use sam_pio_forceclk() so that we can read the current state of an open-drain output in the TWI reset logic.
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2014-07-09 11:31:21 -06:00 |
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Gregory Nutt
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c4b9eaa01f
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Add a new interface sam_pio_forceclk() that can be used to force PIO clocking on. I am afraid I was too conservative with PIO clocking in the initial design; this is the price
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2014-07-09 11:26:07 -06:00 |
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